Segmented Gate CFET Layout for Cross-Coupled Pass Gates
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Solution Overview
Problem
Existing semiconductor device fabrication methods struggle to create both non-stacked and stacked transistor structures with a shared gate, particularly for CMOS and non-CMOS devices, as typical CFET devices lack a pass gate function and require cross-coupling between the gate and source/drain, which is not efficiently achievable.
Innovation Solution
A method involving the formation of sacrificial gates, etching cuts through top channel structures, and replacing them with metal gate stacks, allowing for the creation of both non-stacked and stacked transistors with cross-coupled gate and source/drain contacts, enabling the fabrication of pass gates and CFET devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a common gate electrode is used in CFET devices to reduce footprint, then area efficiency is improved, but the ability to provide pass gate function is lost
Solution Approach 1:
The gate electrode is segmented into two independent gates (first gate and second gate) instead of using a common gate electrode. This segmentation allows each gate to be independently controlled, enabling the first gate to function as a pass gate while the second gate controls the stacked transistor, thus resolving the contradiction between area efficiency and pass gate functionality
Solution Approach 2:
Different regions of the device are assigned different gate configurations: the first transistor structure receives a first gate electrode for pass gate functionality, while the second transistor structure receives a second gate electrode for CFET operation. This local differentiation allows each region to optimize for its specific function while sharing the same vertical stacking architecture
2Device complexity
If monolithic process is used to form stacked transistor structures, then manufacturing complexity is reduced, but the ability to create cross-coupled gate and source/drain connections is limited
Solution Approach 1:
The method performs preliminary actions during the monolithic fabrication process by forming specific opening patterns in the gate electrode at early stages. These preliminary openings are later used to create cross-coupled connections between gates and source/drain regions, enabling complex interconnections while maintaining the simplicity of the monolithic process
Solution Approach 2:
The patent introduces intermediary structures (such as dielectric plugs and opening patterns in the gate electrode) that facilitate cross-coupled connections during the monolithic process. These intermediaries enable the complex wiring required for cross-coupling without requiring additional fabrication steps beyond the standard monolithic flow
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the efficient fabrication of both non-stacked transistor structures suitable for pass gates and stacked structures like CFETs with interconnected gates and source/drain contacts, addressing the limitations of traditional CFET devices by allowing for area-efficient circuit designs and reduced routing layer usage.
Implementation Method 1
forming a cut through the first top channel structure by etching the first top channel structure from the opening in the sacrificial gate
Data Source
Figure 1a~1d
Figure 2a~2d
Figure 3a~3d
AI summary
The disclosure relates to a method for forming a semiconductor device, comprising: forming a first bottom and top channel structures, and second bottom and top channel structures, and a sacrificial gate extending across the channel structures; forming an opening in the sacrificial gate, over the first top channel structure and forming a cut through the first top channel structure; forming a dielectric plug in the cut and the opening; removing the sacrificial gate and subsequently forming an RMG structure comprising a first gate stack on the first bottom channel structure and a second gate stack on the second bottom and top channel structures,; forming pairs of S/D structures on the first bottom channel structure, the second bottom channel structure, and the second top channel structure; forming S/D contacts on the S/D structures; forming a trench for a cross-couple contact by etching a dielectric gate capping layer and a dielectric contact capping layer, the trench extending from the second gate stack, over the dielectric plug, to a first S/D contact on a first S/D structure of the pair of S/D structures on the first bottom channel structure; and forming the cross-couple contact in the trench, the contact interconnecting the second gate stack and the first S/D contact.