Segmented-Gate Transistor for Cryogenic Ohmic Contacts
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Solution Overview
Problem
Achieving low-resistance ohmic electrical contacts in atomically thin semiconductors, such as transition metal dichalcogenides (TMDCs), is challenging, especially at extreme cryogenic temperatures and very low carrier densities, where quantum effects can be investigated.
Innovation Solution
A transistor design with a substrate, contact electrodes, a two-dimensional semiconductor material layer, control gates, and a dielectric layer is implemented, allowing independent tuning of carrier densities at the contact and channel regions to facilitate ohmic contacts, even at low temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistor structures are used with atomically thin semiconductors, then device simplicity is maintained, but achieving low-resistance ohmic contacts at cryogenic temperatures becomes impossible
Solution Approach 1:
The gate structure is segmented into multiple independent gates (first control gate, second control gate, and main gate) that can independently tune carrier densities in different regions of the two-dimensional semiconductor material layer, enabling separate optimization of contact and channel regions
Solution Approach 2:
Different regions of the semiconductor material are given different local properties through independent gate control: contact regions are tuned to have high carrier densities for low-resistance ohmic contacts, while the channel region maintains low carrier densities for quantum effect investigation
2Measurement precision
If carrier density is reduced to investigate quantum effects, then quantum mechanical properties become accessible, but electrical contact resistance increases
Solution Approach 1:
The device is segmented into contact regions and channel region with independently controlled carrier densities, allowing the channel to operate at low carrier densities for quantum effect detection while contact regions operate at high carrier densities for low-resistance electrical connections
Solution Approach 2:
Different local carrier density conditions are created: high carrier density in contact regions for ohmic contacts and low carrier density in the channel region for quantum effect investigation, achieved through independent gate control
3Measurement precision
If temperature is reduced to extreme cryogenic levels, then quantum mechanical properties can be exploited, but achieving reliable electrical contacts becomes extremely difficult
Solution Approach 1:
The contact regions are pre-tuned to high carrier densities through control gates before the device is cooled to cryogenic temperatures, ensuring that ohmic contacts are already optimized and will remain reliable during low-temperature quantum effect measurements
Solution Approach 2:
The device maintains different local temperature responses: contact regions with high carrier densities sustain reliable ohmic contacts at cryogenic temperatures, while the channel region at low carrier densities enables quantum effect measurement
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enables reliable, low-resistance ohmic contacts, enabling the investigation of charge transport and quantum mechanical effects in TMDCs at extremely low channel carrier densities and temperatures below 200 mK.
Implementation Method 1
a dielectric layer separating the main gate, the first control gate and the second control gate from the two-dimensional semiconductor material layer
Data Source
AI summary
Various embodiments may provide a transistor. The transistor may include a substrate, a first contact electrode and a second contact electrode over the substrate. The transistor may additionally include a two-dimensional semiconductor material layer above the substrate such that the first contact electrode is in contact with a first portion and the second contact electrode is in contact with a second portion of the two-dimensional semiconductor material layer. The transistor may further include a first control gate and a second control gate. The transistor may additionally include a main gate over a third portion of the two-dimensional semiconductor material layer, the third portion between the first portion and the second portion. The transistor may also include a dielectric layer separating the main gate, the first control gate and the second control gate from the two-dimensional semiconductor material layer.


