Segmented High-k Gate Dielectric for Low Vt and Leakage
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Solution Overview
Problem
Existing methods for forming gate dielectrics in semiconductor devices face challenges in achieving low threshold voltage (Vt) and small gate leakage current, particularly due to the need for high-temperature drive-in anneals that can cause crystallization of high-k dielectric layers.
Innovation Solution
A method involving the formation of a thin bottom high-k dielectric layer, a first diffusion source layer with metal atoms, and a top high-k dielectric layer, where the metal atoms diffuse into the bottom high-k dielectric layer during a low thermal budget drive-in anneal, creating an interface dipole region that tunes the effective work function and reduces Vt while minimizing gate leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If metal atoms are diffused through a thick high-k dielectric layer using conventional drive-in anneal, then the effective work function is tuned and threshold voltage is controlled, but high temperature and long anneal time are required which cause crystallization of the high-k dielectric layer and increase gate leakage current
Solution Approach 1:
The high-k dielectric layer is divided into two separate layers: a first high-k dielectric layer (thinner, e.g., 1-3 nm) and a second high-k dielectric layer (thicker, e.g., 2-5 nm). The metal atoms are diffused only through the first high-k dielectric layer during drive-in anneal, which reduces the diffusion distance and allows for lower temperature and shorter time processing. This segmentation prevents crystallization of the thicker second high-k dielectric layer while still achieving sufficient metal atom diffusion to tune the effective work function and control threshold voltage.
2Manufacturing precision
If drive-in anneal is performed at high temperature and/or long anneal time to diffuse metal atoms through a thick high-k dielectric layer, then metal atoms can reach the interface to tune effective work function, but crystallization of the high-k dielectric layer occurs resulting in increased gate leakage current
Solution Approach 1:
The high-k dielectric layer is segmented into a first high-k dielectric layer and a second high-k dielectric layer, where the first layer serves as the diffusion path for metal atoms. By making the first layer thinner (1-3 nm compared to the total thickness), the diffusion distance is reduced, allowing metal atoms to reach the interface and tune the effective work function at lower temperatures and shorter times, thereby preventing crystallization of the second high-k dielectric layer and maintaining its amorphous structure.
3Productivity
If a thin bottom high-k dielectric layer is used to reduce diffusion distance for metal atoms, then low temperature and short time drive-in anneal can be used, but the total thickness of high-k dielectric must still be sufficient to provide low gate leakage current
Solution Approach 1:
The high-k dielectric layer is segmented into a first high-k dielectric layer with thickness of 1-3 nm and a second high-k dielectric layer with thickness of 2-5 nm. The first layer provides a short diffusion path for metal atoms during drive-in anneal, enabling low temperature and short time processing (high productivity). The second layer provides additional thickness to the total high-k dielectric structure, ensuring sufficient barrier properties to maintain low gate leakage current (high reliability).
Solution Approach 2:
The problem is solved by transitioning from a single-layer high-k dielectric structure to a multi-layer structure. By adding the vertical dimension of layer stacking, the patent separates the functions: the first layer handles metal atom diffusion (enabling efficient annealing) while the second layer provides the necessary thickness for electrical isolation (reducing gate leakage). This dimensional change allows both requirements to be satisfied simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method achieves a low thermal budget drive-in anneal, reducing the risk of crystallization and resulting in a small gate leakage current and low threshold voltage, while maintaining the quality of the gate dielectric.
Implementation Method 1
performing a first anneal such that metal atoms of the first diffusion source layer diffuse into the bottom high-k dielectric layer
Implementation Method 2
performing a first anneal such that metal atoms of the first diffusion source layer diffuse into the bottom high-k dielectric layer
Data Source
Figure 1a~1b
Figure 1c~1d
Figure 1e~1f
AI summary
The present invention provides a method for forming a gate dielectric (100) for a semiconductor device, the method comprising forming an interfacial layer (102a-b), being a layer of dielectric material, forming a bottom high-k dielectric layer (104a-b) on top of the interfacial layer (102a-b); forming a first diffusion source layer (106a-b), being a layer comprising metal atoms, on top of the bottom high-k dielectric layer (104a-b); forming a first capping layer (108a-b) on top of the first diffusion source layer (106a-b); performing a first anneal such that metal atoms of the first diffusion source layer (106a-b) diffuse into the bottom high-k dielectric layer (104a-b); removing the first capping layer (108a-b) after the first anneal; and forming, after removing the first capping layer (108a-b), a top high-k dielectric layer (120a-b) on top of the bottom high-k dielectric layer (104a-b). The present invention also provides a gate dielectric (100) for a semiconductor device.