Segmented Gate Dielectric Layout for Low-GIDL MV Transistors
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Solution Overview
Problem
The limited thickness of spacers in medium voltage (MV) devices leads to severe gate-induced drain leakage (GIDL) due to hard constraints on pitch, which existing methods struggle to address effectively without impacting the threshold voltage or increasing process costs.
Innovation Solution
The method involves configuring the first gate dielectric layer as a body gate dielectric layer in the middle region and an edge gate dielectric layer on the periphery, allowing the edge gate dielectric layer to increase in thickness without affecting the threshold voltage, thereby reducing GIDL leakage by enhancing the isolation layer and maintaining device speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the spacer thickness is increased to reduce GIDL leakage, then the leakage current is reduced, but the pitch constraint is violated and device integration density decreases
Solution Approach 1:
The gate dielectric layer is segmented into two distinct regions: a body gate dielectric layer in the middle region and an edge gate dielectric layer at the edges. This segmentation allows independent optimization of each region's thickness - the edge gate dielectric layer can be thicker to reduce GIDL leakage, while the body gate dielectric layer maintains appropriate thickness for device operation, thus resolving the contradiction between leakage reduction and pitch constraint
Solution Approach 2:
Different thicknesses of gate dielectric are applied to different locations of the gate structure. The edge gate dielectric layer has a greater thickness than the body gate dielectric layer, providing localized enhancement for leakage reduction at the edges where GIDL is most severe, without compromising the overall device performance and pitch requirements
2Productivity
If the spacer thickness is reduced to meet pitch requirements, then device integration density is improved, but GIDL leakage increases
Solution Approach 1:
By segmenting the gate dielectric into body and edge portions, the patent enables the edge gate dielectric layer to provide sufficient thickness for leakage control even when the overall spacer thickness is reduced to meet pitch requirements, thus maintaining integration density while preventing GIDL leakage
Solution Approach 2:
The edge gate dielectric layer provides localized thickness enhancement specifically where needed for leakage reduction, allowing the overall device structure to maintain compact dimensions for high integration density while the local edge region compensates for leakage issues that would otherwise require increased overall spacer thickness
3Reliability
If the gate dielectric layer thickness is increased to reduce leakage, then GIDL is reduced, but the threshold voltage control is affected
Solution Approach 1:
The gate dielectric layer is divided into a body gate dielectric layer and an edge gate dielectric layer with different thicknesses. The body gate dielectric layer maintains the thickness required for proper threshold voltage control, while the edge gate dielectric layer is thicker to reduce GIDL leakage, thus resolving the contradiction between leakage reduction and threshold voltage precision
Solution Approach 2:
Different thicknesses of gate dielectric are applied to different locations: the body region maintains appropriate dielectric thickness for threshold voltage control, while the edge region has enhanced thickness specifically for leakage reduction, allowing independent optimization of both threshold voltage precision and leakage current
Data Source
AI summary
The present application discloses an MV device, wherein a first gate structure of the MV device is formed by stacking a first gate dielectric layer and a first gate conductive material layer. The first gate dielectric layer is divided into a body gate dielectric layer and an edge gate dielectric layer. The body gate dielectric layer is located in a middle region, and the edge gate dielectric layer surrounds the periphery of the body gate dielectric layer. A channel region is located in a surface of the semiconductor substrate between the lightly doped drain regions on the two sides of the first gate structure. In a channel length direction, the top of the channel region is covered by the body gate dielectric layer. The present application also discloses a method for manufacturing the MV device.