Segmented Gate Structure to Prevent HKMG Planarization Dishing
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Solution Overview
Problem
The integration of high-voltage devices with high-k metal gate (HKMG) technology in semiconductor integrated circuits faces challenges due to the dishing effect during planarization processes, which degrades the performance of high-voltage devices.
Innovation Solution
A semiconductor structure and method that involves forming a dielectric structure within the high-voltage gate structure, providing structural support to reduce or eliminate the dishing effect, thereby improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If planarization process is used to integrate high-voltage devices with HKMG logic core, then device integration is achieved, but dishing effect occurs which degrades device performance
Solution Approach 1:
The gate structure is segmented into multiple regions: HKMG logic core regions with high-k metal gate electrodes and high-voltage device regions with polysilicon gate electrodes. This segmentation allows each region to be optimized independently, preventing the dishing effect from degrading overall device performance while maintaining high-level device integration on the same chip.
Solution Approach 2:
Different gate structures are applied to different regions of the chip: high-k metal gate electrodes for logic core regions requiring high performance and polysilicon gate electrodes for high-voltage device regions. This local quality approach ensures that each region has the appropriate structure for its function, eliminating the dishing effect in high-voltage regions while maintaining integration.
2Productivity
If feature size is decreased to increase functional density, then more devices per chip area are achieved, but dishing effect during planarization worsens
Solution Approach 1:
The patent applies different gate electrode materials and structures to different regions: polysilicon gates in high-voltage device regions and high-k metal gates in logic core regions. This local differentiation allows small feature sizes to be maintained in logic cores while preventing dishing-related precision degradation in high-voltage regions through appropriate material selection.
Data Source
AI summary
A semiconductor structure and forming method thereof are provided. The semiconductor structure includes a substrate, a gate dielectric, a gate electrode and dielectric structures. The gate dielectric has a top surface aligned with a top surface of the substrate. The gate electrode is disposed over the substrate and overlaps the gate dielectric. The gate electrode has first segments extending in parallel along a direction. The dielectric structures are disposed over the substrate, overlap the gate dielectric and extend in parallel along the direction. The dielectric structures and the first segments are arranged in an alternating pattern.