Segmented Gate Insulating Film Layout for Hot-Carrier and ESD Control

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Solution Overview

Problem

Transistors with single-gate and multi-gate structures face issues such as hot carrier injection and electro-static discharge (ESD), which can lead to performance degradation and reduced yield.

Innovation Solution

A transistor design featuring a semiconductor portion with a gate insulating film having varying thick portions, including a first thick portion, a second thick portion with the same film thickness, a third thick portion with a larger film thickness, and additional thick portions, strategically positioned to overlap electrodes and the semiconductor portion, thereby reducing hot carrier injection and ESD.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single-gate structure is used, then device complexity is reduced, but hot carrier injection occurs causing performance degradation

Engineering Contradiction:

Improvegate structure complexityVSAvoidtransistor performance stability

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The gate insulating film is segmented into multiple regions with different thicknesses (first thick portion, second thick portion, third thick portion) along the channel length direction. This segmentation allows different portions of the channel to experience different electric field strengths, suppressing hot carrier injection while maintaining manageable device complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the gate insulating film are given different local qualities through varying thickness. The first thick portion is positioned near the source, the second thick portion near the drain, and the third thick portion in between, creating localized electric field control that prevents hot carrier injection without requiring complex multi-gate structures.

Inventive Principle:

Principle #3Local quality

2Device complexity

If a single-gate structure is used, then device complexity is reduced, but ESD occurs damaging gate metal and channel material

Engineering Contradiction:

Improvegate structure complexityVSAvoidelectro-static discharge damage

Core Design Contradiction:

Device complexityVSObject-affected harmful factors

Solution Approach 1:

The gate insulating film is designed with beforehand cushioning by creating thicker portions (first thick portion near source, second thick portion near drain) at locations prone to ESD. These thicker regions act as protective cushions that prevent ESD from reaching and damaging the gate metal and channel material, while the overall single-gate structure maintains low device complexity.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

3Reliability

If a multi-gate structure is used, then hot carrier injection is suppressed, but the number of end portions increases causing more ESD occurrences

Engineering Contradiction:

Improvehot carrier injection suppressionVSAvoidelectro-static discharge frequency

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

Rather than using multiple separate gates, the invention segments the gate insulating film itself into different thickness regions along the channel. This achieves hot carrier injection suppression through localized electric field control while avoiding the creation of multiple gate end portions that would increase ESD risk.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The gate insulating film exhibits local quality variations in thickness to suppress hot carrier injection in specific channel regions, while the continuous gate structure maintains few end portions, thereby reducing ESD occurrence compared to multi-gate structures.

Inventive Principle:

Principle #3Local quality

4Manufacturing precision

If uniform gate insulating film thickness is used, then manufacturing precision is simplified, but both hot carrier injection and ESD cannot be effectively suppressed

Engineering Contradiction:

Improvegate insulating film thickness controlVSAvoidtransistor performance stability

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The gate insulating film is designed with local quality variations through different thickness portions (first thick portion, second thick portion, third thick portion) positioned at specific locations. This allows effective suppression of hot carrier injection and ESD while maintaining relatively simple manufacturing processes, as the thickness variation can be achieved through standard photolithography and etching techniques with appropriate mask design.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20250126844A1Transistor and manufacturing method for transistor

Publication Date: 2025.04.17 SHARP DISPLAY TECHNOLOGY CORP

AI summary

A gate insulating film includes a first thick portion and a second thick portion having the same film thickness, and a third thick portion, a fourth thick portion, and a fifth thick portion all having a film thickness larger than a thickness of the first thick portion, the first thick portion and the second thick portion overlap both the first electrode and a semiconductor portion and are disposed at positions spaced apart from each other in a first direction, the third thick portion is interposed between the first thick portion and the second thick portion, and the fourth thick portion and the fifth thick portion are disposed to overlap both the semiconductor portion and both end portions of a first electrode.