Segmented Gate IGBT Reduces Switching Losses
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Solution Overview
Problem
Semiconductor devices, particularly IGBTs, face challenges in minimizing switching losses due to inefficiencies in controlling current and breakdown voltage, which affect their performance as power semiconductor devices.
Innovation Solution
The semiconductor device design incorporates a specific configuration with first and second gate electrodes, insulating films, and semiconductor layers arranged in a manner that controls the discharge of holes and carrier behavior, reducing switching losses by optimizing the width and height of mesa portions and using different gate voltages to manage channel formation and discharge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional IGBT structure is used, then device simplicity is maintained, but switching losses increase due to inefficient current control and carrier discharge
Solution Approach 1:
The gate electrode structure is segmented into multiple independent gate electrodes (first gate electrode and second gate electrode) that can be controlled separately. This segmentation allows independent control of carrier discharge in different regions, optimizing switching performance and reducing switching losses while managing the increased structural complexity.
Solution Approach 2:
Different gate electrodes are applied with different gate voltages to create localized control over channel formation and carrier discharge. The first gate electrode controls one region while the second gate electrode controls another region, enabling optimized local carrier management that reduces overall switching losses.
2Strength
If single gate electrode configuration is used, then device structure is simple, but breakdown voltage control is insufficient
Solution Approach 1:
The gate electrode is divided into multiple segmented gates that can be independently controlled. This segmentation enables different voltage applications across different regions, providing enhanced control over breakdown voltage characteristics while managing the increased structural complexity through modular design.
3Loss of energy
If optimized mesa portion dimensions are used, then switching losses are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The invention optimizes specific geometric parameters of the mesa portions (width and height ratios) to achieve reduced switching losses. By carefully controlling the width in the second direction and height, the device achieves better carrier discharge efficiency and reduced switching losses while maintaining manufacturability through defined parameter ranges.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces switching losses and improves breakdown voltage, leading to lower on-voltage and reduced energy losses during operation, enhancing the overall performance of the semiconductor device and module.
Implementation Method 1
a first gate voltage different from a second gate voltage are applied to a first gate pad and a second gate pad, respectively. Accordingly, carriers are discharged, and thus switching losses are reduced.
Implementation Method 2
A first insulating film is between the first gate electrode and the first semiconductor layer. A second insulating film is between the second gate electrode and the first semiconductor layer.
Data Source
AI summary
A semiconductor device includes first and second electrodes. A first-type layer is between the first and second electrodes. A pair of first gate electrodes is between the first and second electrodes and each is surrounded by a gate insulating film. Second gate electrodes are disposed between the pair of first gate electrodes. A second-type layer is on the first-type layer in a first region between a first gate electrode and one of the second gate electrodes. Another first-type layer is on the second-type layer. This other first-type layer is directly adjacent to the gate insulating film. Another second-type layer is on the other second-type layer. A width of the first-type layer between adjacent second gate electrodes is less than a length of the first-type layer in the region between adjacent second gate electrodes.