Segmented Gate Isolation Structure for Gate Fill Window Control
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Solution Overview
Problem
As semiconductor devices shrink, parasitic capacitance between adjacent gate structures in multi-gate transistors increases, slowing down switching speed and reducing the gate fill window, which complicates the formation of satisfactory gate structures and lowers yield.
Innovation Solution
A method is introduced to form a gate isolation structure by depositing gate structure layers over a dielectric fin, planarizing, and then removing the dielectric fin to create an isolation trench, allowing the gate isolation structure to be in direct contact with gate electrode layers, thereby reducing parasitic capacitance without sacrificing the gate fill window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the width of gate cut feature or dielectric fin is increased to reduce parasitic capacitance, then parasitic capacitance is reduced, but the gate fill window is reduced making it difficult to form satisfactory gate structures
Solution Approach 1:
The isolation structure is divided into two distinct portions: a lower portion that provides parasitic capacitance reduction and an upper portion that maintains gate fill window. This segmentation allows each portion to optimize for its specific function without compromising the other.
Solution Approach 2:
The invention transitions from a single-width dielectric fin to a multi-dimensional isolation structure with varying width along the vertical dimension. The lower portion has a first width while the upper portion has a second width, utilizing the vertical dimension to resolve the horizontal trade-off between capacitance reduction and gate formation.
2Device complexity
If conventional gate cut features or dielectric fins are used, then gate structure formation is simplified, but parasitic capacitance between adjacent gate structures increases
Solution Approach 1:
The isolation structure is divided into two distinct portions: a lower portion that provides parasitic capacitance reduction and an upper portion that maintains gate fill window. This segmentation allows each portion to optimize for its specific function without compromising the other.
Solution Approach 2:
Different portions of the isolation structure have different widths optimized for different functions: the lower portion has a larger width for capacitance reduction while the upper portion has a smaller width for gate formation accessibility. This local quality variation resolves the global trade-off.
Data Source
AI summary
A semiconductor device according to the present disclosure includes a first gate structure and a second gate structure aligned along a direction, a first metal layer disposed over the first gate structure, a second metal layer disposed over the second gate structure, and a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer.