Segmented Gate Semiconductor Layout for Low Resistance and Capacitance
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Solution Overview
Problem
Existing semiconductor devices face a trade-off between reducing on-resistance and capacitance, as increasing the integration or chip area to lower on-resistance often increases capacitance, while thickening the gate insulating film to reduce capacitance increases on-resistance.
Innovation Solution
A semiconductor device structure with a field insulating film and gate extension portion that separates gate portions, increasing channel region area and reducing capacitance by spacing apart gate electrodes, while maintaining a closed well and channel region configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If high integration or large chip area is used to lower on-resistance, then on-resistance is reduced, but capacitance increases
Solution Approach 1:
The gate structure is divided into multiple gate portions (first gate portion, second gate portion, third gate portion) that are spaced apart from each other. This segmentation allows the device to achieve low on-resistance through increased channel area while the spaced-apart gates reduce capacitance by preventing overlapping between gate electrodes and channel regions.
Solution Approach 2:
The patent introduces a field insulating film and gate extension portions that extend in directions intersecting the main channel direction. This dimensional approach allows the channel region to extend in multiple directions (increasing effective channel area for low on-resistance) while the gate portions remain spaced apart in the vertical dimension to reduce capacitance.
2Quantity of substance
If gate insulating film is made thicker to reduce capacitance, then capacitance is reduced, but on-resistance increases
Solution Approach 1:
Instead of thickening the gate insulating film uniformly, the patent segments the gate into multiple portions spaced apart. This segmentation reduces capacitance through increased physical separation between gate electrodes and channel regions, while maintaining thin gate insulating films to preserve low on-resistance characteristics.
Solution Approach 2:
Field insulating films are introduced as intermediary elements between the gate portions and channel regions. These field insulating films reduce capacitance by providing electrical isolation, while the gate extension portions act as intermediaries to extend the channel region without requiring thicker gate insulating films.
3Quantity of substance
If gate portions are separated to reduce capacitance, then capacitance is reduced, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into the field insulating film and gate extension portions. The field insulating film serves both as an electrical isolator to reduce capacitance and as a structural element that supports the gate extension portions. The gate extension portions simultaneously extend the channel region and maintain the spaced-apart gate configuration, reducing the need for additional separate components.
Data Source
AI summary
A semiconductor device comprising, a substrate comprising a cell region, a first well region in the cell region of the substrate, a second well region disposed in the cell region and spaced apart from the first well region in a first direction, a third well region disposed in the cell region and spaced apart from the first well region in a second direction intersecting the first direction, a first gate portion disposed in overlap with a part of the first well region and a part of the third well region, and a second gate portion disposed in overlap with a part of the second well region, wherein the first gate portion and the second gate portion are spaced apart from each other.