Segmented Gate Oxide Structure for Low On-Resistance Semiconductors
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Solution Overview
Problem
Existing semiconductor structures face challenges in optimizing on-resistance performance without compromising linear-region drain current or increasing source-to-drain pitch, especially when gate and drain voltages differ.
Innovation Solution
The implementation of a Resurf (Reduced Surface Electric Field) oxide over the N-well region, combined with a thickened gate oxide extending towards the drain region, optimizes on-resistance performance while maintaining or enhancing on-mode current and reducing the source-to-drain pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate oxide structure is used, then manufacturing process is simple, but on-resistance is high
Solution Approach 1:
The gate oxide is divided into two distinct portions: a first portion over the channel region and a second portion over the drain region. This segmentation allows each portion to be optimized independently, with the second portion having a greater thickness to reduce surface electric field and on-resistance in the drain area without affecting the channel performance.
Solution Approach 2:
Different thicknesses of gate oxide are applied to different regions of the semiconductor device. The gate oxide over the drain region is thicker than over the channel region, providing localized electric field reduction where needed while maintaining proper channel control and performance.
2Reliability
If gate oxide thickness is increased to reduce on-resistance, then on-resistance decreases, but linear-region drain current is compromised
Solution Approach 1:
The gate oxide is segmented into different thickness regions: a thinner first portion over the channel to maintain proper channel control and current drive, and a thicker second portion over the drain to reduce on-resistance. This segmentation resolves the contradiction by applying different thicknesses in different locations rather than uniformly increasing thickness.
Solution Approach 2:
The gate oxide structure implements local quality by having different thicknesses in different regions. The thicker gate oxide is localized to the drain region where electric field reduction is needed, while the channel region maintains its original gate oxide thickness to preserve linear-region drain current characteristics.
3Reliability
If conventional oxide structure is used, then source-to-drain pitch is maintained, but on-resistance performance is insufficient
Solution Approach 1:
The invention addresses on-resistance performance by modifying the gate oxide structure in the vertical dimension (thickness) rather than changing the horizontal source-to-drain pitch. By increasing gate oxide thickness over the drain region, the patent reduces on-resistance through electric field management in a different dimension, keeping the source-to-drain pitch unchanged.
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of well regions, a gate structure, a drain region, a source region, a circuit, and a voltage source. The gate structure includes a gate oxide over a first surface of the substrate and a gate electrode over the gate oxide. The gate oxide includes a first portion and a second portion connected with the first portion, wherein a thickness of the second portion is greater than that of the second portion. The voltage source is coupled to the drain region, configured to provide a first voltage to the drain region. The circuit is coupled to the gate structure, configured to provide a second voltage to the gate structure. A ratio of the first voltage to the second voltage is in a range from 2 to 4. Methods for manufacturing the semiconductor structure are also provided.