3D Memory Fabrication via Segmented Gate Pillars
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Solution Overview
Problem
The increasing complexity of three-dimensional memory devices leads to common defects such as bit line channel bending and word line bridging during the fabricating process due to high aspect ratios and stacking of composite films.
Innovation Solution
A method for fabricating memory devices involves forming a stack layer with alternating insulating and conductive layers, creating gate pillar structures and dielectric pillars that are alternately arranged to divide the stack layer into separate structures, which are then embedded using separate etching and deposition processes to prevent bit line channel bending and word line bridging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If three-dimensional memory devices are made smaller in size with greater integrality, then storage capability is improved, but defects such as bit line channel bending and word line bridging occur more commonly
Solution Approach 1:
The patent divides the continuous bit line channel into multiple segmented channels by introducing isolation structures between adjacent memory holes. This segmentation prevents the bending of bit line channels that occurs in continuous structures, thereby improving manufacturing precision while maintaining the three-dimensional stacked architecture for high storage capability
Solution Approach 2:
The patent introduces isolation structures as intermediary elements between adjacent word lines and bit line channels. These isolation structures act as mediators that prevent direct contact and potential bridging between conductive elements, thereby reducing fabrication defects while enabling higher device integrality
2Productivity
If high aspect ratio and stacking of composite films are used to increase integrality, then device density is improved, but fabricating process defects increase
Solution Approach 1:
The patent segments the composite film structure by introducing isolation structures at specific intervals within the stacked layers. This segmentation allows the maintenance of high aspect ratio and multiple stacking layers for improved device density, while preventing the propagation of defects through the continuous film structure
Solution Approach 2:
The patent applies different material properties and structural characteristics to different regions of the device. Isolation structures are strategically placed in specific locations where defect prevention is most critical, allowing local optimization of manufacturing precision without compromising overall device density
Data Source
AI summary
Provided is a method for fabricating a memory device including forming a stack layer on a substrate, and embedding a plurality of gate pillar structures and a plurality of dielectric pillars in the stack layer. The plurality of gate pillar structures and the plurality of dielectric pillars extend along a same direction and are alternately arranged, so that the stack layer is divided into a plurality of stack structures.