Segmented Gate Transistors for NAND Memory
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Solution Overview
Problem
Existing field effect transistors (FETs) lack optimization in terms of gate material distribution over channel regions, leading to suboptimal performance in applications like NAND memory arrays, where higher threshold voltage and reduced resistance-capacitance (RC) are desired.
Innovation Solution
The use of FETs with gates comprising two or more different conductive materials, each covering separate segments of the channel region, allowing for tailored electrical properties and improved integration in highly integrated circuitry, such as vertical NAND strings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional single-material gates are used in FETs, then the device structure is simple, but the threshold voltage control and RC characteristics are suboptimal
Solution Approach 1:
The gate is divided into multiple segments along the channel region, with each segment having a different conductive material. This segmentation allows independent optimization of threshold voltage control in different regions, resolving the contradiction by enabling better electrical characteristics without requiring complete redesign of the entire gate structure.
Solution Approach 2:
Different conductive materials are applied to different segments of the gate to provide locally optimized electrical properties. This allows specific regions to have tailored conductivity and threshold voltage characteristics, improving overall device performance while maintaining a manageable structural complexity through targeted material placement.
2Reliability
If conventional single-material gates are used in FETs, then the manufacturing process is simpler, but the resistance-capacitance (RC) characteristics are not optimized
Solution Approach 1:
The gate fabrication process is segmented into multiple deposition steps, each applying a different conductive material to specific regions. This approach optimizes RC characteristics by allowing selective material placement while keeping the manufacturing process broken down into manageable, sequential steps that can be integrated into existing fabrication workflows.
Solution Approach 2:
The gate structure uses composite materials comprising multiple conductive materials with different electrical properties. This composite approach optimizes RC characteristics by combining materials with complementary properties, while the manufacturing complexity is managed through standardized deposition techniques applied in sequence.
3Reliability
If larger FET devices are used to achieve desired electrical performance, then the electrical characteristics are improved, but the device footprint increases
Solution Approach 1:
Different conductive materials are placed in specific gate segments to locally enhance electrical characteristics such as threshold voltage control and conductivity. This allows smaller device dimensions to achieve the same or better electrical performance, reducing footprint while maintaining reliability.
Solution Approach 2:
The electrical parameters of the gate are optimized by changing the material composition and distribution across different segments. This enables achieving desired electrical characteristics in a compact configuration, improving the performance-to-footprint ratio by precisely controlling electrical parameters through material selection and placement.
Data Source
AI summary
Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.