Segmented HVFET Pillar Layout Relieves Wafer Warping
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Solution Overview
Problem
Conventional vertical high-voltage field-effect transistor (HVFET) structures experience significant warping of silicon wafers during high-temperature processing steps, leading to permanent deformation that prevents tool handling and affects subsequent processing.
Innovation Solution
The HVFET structure is segmented into multiple sections separated by dummy silicon pillars or pillars made of different materials to relieve mechanical stress, preventing warping and damage, while maintaining adequate conduction area through optimized layout and material selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a continuous silicon pillar structure is used in vertical HVFET, then the conduction area is maximized, but significant warping occurs during high-temperature processing
Solution Approach 1:
The continuous silicon pillar structure is divided into multiple discrete pillars arranged in an array. This segmentation reduces the overall warping by distributing thermal stress across multiple smaller structures rather than one large continuous structure, while maintaining adequate total conduction area through optimized pillar density and dimensions.
2Shape
If dummy silicon pillars are introduced to relieve mechanical stress, then warping is reduced, but device complexity increases
Solution Approach 1:
The dummy pillars are merged with the functional pillar array to form a unified structure. The dummy pillars are positioned at the corners and edges of the array, serving dual purposes: relieving mechanical stress to reduce warping and maintaining structural integrity of the overall device layout.
Data Source
AI summary
In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.