Segmented Hybrid Gate Cuts for Stacked Transistor Isolation
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Solution Overview
Problem
Existing gate cut processes in stacked field effect transistor (FET) fabrication face challenges in efficiently isolating neighboring CMOS cells, leading to potential electrical connections between devices that can affect device performance and diversity.
Innovation Solution
A method involving the formation of a first and second stack of nanosheets, with a lower gate cut structure between the lower nanosheets, followed by the deposition of a gate stack and the formation of an upper gate cut structure, allowing for flexible isolation and separation of neighboring CFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single gate cut process is used to isolate neighboring CMOS cells, then the fabrication process is simple, but electrical isolation between stacked transistors is insufficient
Solution Approach 1:
The gate cut structure is divided into two independent segments: a lower gate cut formed between lower nanosheets before gate stack formation, and an upper gate cut formed between upper nanosheets after gate stack formation. This segmentation provides comprehensive electrical isolation at multiple levels, resolving the contradiction by enhancing isolation reliability through structural division rather than relying on a single complex gate cut.
2Adaptability or versatility
If gate cut structures are formed to isolate neighboring CFETs, then electrical connection control is improved, but the fabrication process complexity increases
Solution Approach 1:
The lower gate cut structure is formed in advance during the nanosheet fabrication process, before the gate stack is deposited. This preliminary action establishes the isolation framework early, allowing subsequent gate stack formation to proceed uniformly across all regions. The upper gate cut is then formed after gate stack deposition to complete the isolation. This staged approach enables device diversity while maintaining manufacturing ease by integrating gate cuts into existing process steps rather than adding separate complex isolation processes.
3Reliability
If neighboring CMOS cells are isolated using traditional gate cut methods, then manufacturing is simple, but device performance is affected due to potential electrical connections
Solution Approach 1:
The formation of lower and upper gate cut structures is merged with the existing nanosheet and gate stack fabrication processes. The lower gate cut is integrated into the nanosheet formation sequence, and the upper gate cut is integrated into the gate stack formation sequence. This merging approach achieves comprehensive electrical isolation for improved device performance without requiring separate dedicated isolation process steps, thereby maintaining fabrication efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables effective isolation of neighboring CFETs, allowing for the fabrication of diverse devices by controlling the electrical connections between them, thereby improving device performance and flexibility.
Implementation Method 1
A lower gate cut structure is formed between the lower first nanosheets and the lower second nanosheets
Implementation Method 2
The first work function metal layer is etched back to expose the upper first nanosheets and the upper second nanosheets to form a lower work function metal layer
Implementation Method 3
Dielectric plugs are formed between the lower work function metal layer and the lower gate cut structure
Data Source
AI summary
Semiconductor devices and methods of forming the same include forming a first stack of nanosheets in a first region, the first stack of nanosheets including upper first nanosheets and lower first nanosheets. A second stack of nanosheets is formed in a second region, the second stack of nanosheets including upper second nanosheets and lower second nanosheets. A lower gate cut structure is formed between the lower first nanosheets and the lower second nanosheets. A gate stack is formed on the first and second stack of nanosheets after forming the lower gate cut structure. An upper gate cut structure is formed after forming the gate stack.