Image Sensor Module With Segmented ISP Chip
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Solution Overview
Problem
CMOS image sensors integrated with image signal processing chips on a single substrate face issues with digital noise affecting the image sensor performance, limiting the integration level and efficiency.
Innovation Solution
The image sensor module comprises an image sensor chip and an image signal processing chip manufactured using CMOS processes with different minimum feature sizes, where the image signal processing chip has a higher aspect ratio and smaller metal line features, reducing digital noise impact and enhancing integration, and they are connected via bonding wires, solder bumps, or through-silicon vias to a PCB, allowing for separate optimization of each chip's design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a CMOS image sensor and an ISP are implemented on one chip using one substrate, then integration is achieved, but digital noise occurring in the ISP affects the CMOS image sensor
Solution Approach 1:
The patent divides the image sensor system into two separate chips: an image sensor chip and an image signal processing chip. This segmentation allows each chip to be optimized independently and prevents digital noise from the ISP from affecting the image sensor, while still achieving functional integration through electrical connection to a common PCB.
Solution Approach 2:
The image signal processing function is extracted from the image sensor chip and placed on a separate ISP chip. This extraction removes the source of digital noise from proximity to the sensitive image sensor, eliminating the harmful interference while maintaining the ability to process images through the separate chip connected to the PCB.
2Device complexity
If the image signal processing chip uses smaller minimum feature size, then the degree of integration is increased, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different minimum feature sizes to different chips based on their specific requirements. The image signal processing chip uses a smaller minimum feature size (e.g., 40nm or 28nm CMOS process) to achieve high integration and advanced processing functions, while the image sensor chip uses a larger minimum feature size (e.g., 90nm or 65nm CMOS process) that is optimized for its specific manufacturing and performance requirements. This local optimization allows each chip to achieve its best possible performance without compromising the other.
Data Source
AI summary
An image sensor module is provided. The image sensor module includes a printed circuit board (PCB), an image sensor chip disposed on a first plane of the PCB and electrically connected to the PCB, and an image signal processing chip disposed on the first plane of the PCB and electrically connected to the PCB. An aspect ratio of the image signal processing chip is at least two times greater than an aspect ratio of the image sensor chip. A minimum feature size of a metal line implemented in the image sensor chip is at least 1.5 times greater than a minimum feature size of a metal line implemented in the image signal processing chip.