Segmented Insulator Structure for NAND Memory Charge Trapping
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Solution Overview
Problem
Current NAND memory cell architectures face challenges in effectively trapping and retaining charge carriers while preventing undesired back-migration and parasitic trapping, particularly in deeply-trapped charges during erase operations.
Innovation Solution
Incorporating a charge-passage structure within the insulator material between the channel and charge-storage materials, comprising a first material closest to the channel, a second material with a specific thickness and composition, and a third material furthest from the channel, to facilitate efficient charge trapping and removal during programming and erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a simple insulator material is used between channel and charge-storage materials, then manufacturing is easier, but charge trapping reliability and erase performance deteriorate
Solution Approach 1:
The insulator material is segmented into multiple distinct layers: a first insulator layer adjacent to the channel material, a second insulator layer adjacent to the charge-storage material, and an intermediate layer between them. This segmentation allows each layer to be optimized for specific functions (charge passage, charge blocking, interface protection) thereby improving overall charge trapping reliability without using a single complex material system
Solution Approach 2:
An intermediate layer is introduced between the first and second insulator layers to serve as a mediator. This intermediate layer prevents direct interaction between the channel and charge-storage materials while allowing controlled charge passage, improving erase performance by preventing parasitic trapping and back-migration without requiring the insulator structure to simultaneously perform conflicting functions
2Reliability
If insulator thickness is increased to prevent back-migration, then charge retention improves, but erase operation efficiency deteriorates
Solution Approach 1:
Different regions of the insulator structure have different local properties: the first insulator layer has properties optimized for allowing charge passage during erase operations (thinner or more conductive), while the second insulator layer has properties optimized for blocking charge back-migration (thicker or more insulative). This local differentiation resolves the contradiction by allowing charge retention without sacrificing erase efficiency
Solution Approach 2:
The insulator is divided into functional segments where the first layer proximity to the channel enables efficient charge removal during erase, while the second layer proximity to the charge-storage material ensures reliable charge retention. The segmentation allows each segment to optimize for its specific function rather than requiring a uniform thickness that compromises both functions
3Reliability
If conventional NAND architecture is used, then device simplicity is maintained, but charge trapping and retention performance deteriorates
Solution Approach 1:
The memory cell structure is segmented into distinct functional regions with specialized insulator layers between the channel and charge-storage materials. This segmentation improves charge trapping and retention by providing controlled interfaces and preventing parasitic effects, while maintaining overall architectural simplicity through systematic layering rather than complex three-dimensional structures
Solution Approach 2:
The insulator structure uses composite material architecture with different insulator layers having different properties optimized for specific functions. This composite approach improves charge retention and trapping reliability by combining materials that excel at different tasks (charge passage, charge blocking, interface protection) without requiring a single complex material system
Data Source
AI summary
A memory cell comprises, in the following order, channel material, a charge-passage structure, programmable material, a charge-blocking region, and a control gate. The charge-passage structure comprises a first material closest to the channel material, a third material furthest from the channel material, and a second material between the first material and the third material. The first and third materials comprise SiO2. The second material has a thickness of 0.4 nanometer to 5.0 nanometers and comprises SiOx, where “x” is less than 2.0 and greater than 0. Other embodiments are disclosed.