Segmented Semiconductor Interconnect for Low-Defect Vertical Routing
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Solution Overview
Problem
As semiconductor devices shrink, the increased risk of manufacturing defects in high-aspect ratio monolithic vias affects transistor performance, leading to issues with parasitic capacitance and switching speed due to fill errors and void formation during metal fill of contacts.
Innovation Solution
A spatially-efficient interconnect structure featuring bridge pillars that electrically connect circuit elements across a base isolation layer, reducing the need for additional conductive lines and signal-routing vias, and utilizing a segmented interconnect structure with bridge pillars and metal electrodes to enhance connectivity without increasing lateral distance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-aspect ratio monolithic vias are used to connect circuit elements across isolation layers, then vertical connectivity is achieved, but manufacturing defects such as fill errors and void formation increase
Solution Approach 1:
The interconnect structure is divided into multiple segments: bridge pillars that extend through the base isolation layer, metal electrodes, and signal-routing vias. This segmentation replaces the single high-aspect ratio monolithic via with multiple lower-aspect ratio components, reducing manufacturing complexity and defect rates while maintaining vertical connectivity functionality.
2Reliability
If additional conductive lines and signal-routing vias are added to enhance connectivity, then electrical connection reliability improves, but lateral distance and device area increase
Solution Approach 1:
The bridge pillars extend vertically through the base isolation layer, utilizing the vertical dimension to establish electrical connections between circuit elements on opposite sides. This vertical routing approach avoids the need for additional lateral conductive lines and signal-routing vias, maintaining electrical connection reliability while preserving compact device area.
3Productivity
If transistor dimensions are reduced to increase transistor density, then device capacity increases, but manufacturing defect impact on performance worsens
Solution Approach 1:
The interconnect structure is segmented into bridge pillars, metal electrodes, and signal-routing vias, where each segment has reduced aspect ratio compared to a monolithic via. This segmentation reduces sensitivity to manufacturing defects while enabling continued transistor scaling and density improvement.
4Manufacturing precision
If bridge pillars and metal electrodes are used instead of monolithic vias, then void formation and fill errors are reduced, but manufacturing process complexity increases
Solution Approach 1:
The interconnect structure is divided into multiple fillable segments (bridge pillars, metal electrodes, signal-routing vias) with lower aspect ratios, improving metal fill accuracy and reducing void formation. The segmented approach maintains ease of manufacture by using standard deposition and etching processes applied to multiple smaller features rather than one large high-aspect ratio via.
Data Source
AI summary
A semiconductor device includes a base isolation layer, a first transistor with a first source electrode at a first side of the base isolation layer. A bridge pillar extends through the base isolation layer, and a metal electrode electrically connects the bridge pillar to the first source electrode. The metal electrode and the first source electrode are at the same side of the base isolation layer. A second metal electrode at an opposite side of the base isolation layer electrically connects to the bridge pillar and to a conductive line at the second side of the base isolation layer.