Segmented Interface Layer for Gate Oxide Reliability in Power Devices
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Solution Overview
Problem
Traditional power MOSFETs and IGBTs face challenges with high electrical fields at the gate oxide in the center of the junction field effect (JFET) region, leading to potential gate oxide failure and hot carrier injection during long-term blocking operations, especially under high positive bias conditions.
Innovation Solution
The introduction of an interface layer with segments of hydrogen, nitrogen, boron, phosphorous, lanthanum, strontium, and barium, which is selectively applied between the gate insulating pattern and the semiconductor layer structure, ensuring a reduced dopant concentration at the center of the gate region where the electric field is highest, thereby enhancing interface protection and preventing degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a continuous interface layer is applied across the entire gate region, then interface protection is improved, but the electrical field concentration at the center of the JFET region is not reduced, leading to potential gate oxide failure and hot carrier injection
Solution Approach 1:
The interface layer is divided into multiple segments (first segment, second segment, and optional third segment) positioned at different locations relative to the gate insulating pattern. The first and second segments are positioned adjacent to opposite sides of the gate insulating pattern, while the third segment (when present) is positioned between them. This segmentation allows the interface layer to provide protection without creating a continuous path that would concentrate electrical fields at the center of the JFET region, thereby resolving the contradiction between providing interface protection and reducing electrical field concentration.
Solution Approach 2:
The interface layer is selectively positioned to provide local protection where needed most. The first and second segments are positioned adjacent to the sides of the gate insulating pattern where interface states are most problematic, while intentionally leaving the center region over the JFET region without interface layer material. This local quality approach provides protection at critical interfaces while avoiding the harmful effect of electrical field concentration at the center, thus resolving the contradiction between improving interface protection and reducing harmful electrical field effects.
2Reliability
If an interface layer is applied to protect the gate interface, then interface quality is improved, but the complexity of the manufacturing process increases due to additional deposition and patterning steps
Solution Approach 1:
The interface layer formation process is segmented into multiple deposition steps, with each step forming a specific segment of the interface layer. The first interface layer segment is deposited and patterned, then the second segment is deposited and patterned, and optionally a third segment is deposited between them. This segmented approach allows for better process control and integration with existing manufacturing steps, making the additional complexity manageable while achieving superior interface quality.
Solution Approach 2:
The interface layer segments are formed in advance of final device assembly, with each segment being deposited and positioned before subsequent processing steps. The first and second segments are formed adjacent to the gate insulating pattern sides, and the third segment is formed between them, all before final device completion. This preliminary action allows the interface layer to be integrated into the manufacturing flow without requiring complex post-processing steps, thus improving interface quality while managing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability of the gate regions in power transistors by reducing the risk of gate oxide breakdown and hot carrier injection, maintaining device stability under high-field blocking conditions while maintaining low on-state resistance.
Implementation Method 1
performing an anneal operation so as to diffuse a portion of the interface material along the interface between the gate insulating pattern and the semiconductor layer structure to form an interface layer of the interface material
Data Source
AI summary
A semiconductor device includes a semiconductor layer structure, a gate insulating pattern on the semiconductor layer structure, a gate electrode on the gate insulating pattern, and an interface layer between the gate insulating pattern and the semiconductor layer structure, the interface layer having a first segment and a second segment with a gap therebetween.