Segmented Interpolation DAC Circuit for 16-Bit Accuracy
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Solution Overview
Problem
Conventional digital-to-analog converter (DAC) circuits for microcontrollers face challenges in achieving high accuracy (e.g., 16-bit resolution) due to increased complexity, cost, and calibration requirements, often necessitating a large number of switches and interpolation amplifiers, which complicates the circuit design and increases die costs.
Innovation Solution
A segmented DAC circuit utilizing an interpolation resistor DAC (RDAC) with a resistor-two-resistor (R-2R) DAC and a resistor ladder, combined with a buffer amplifier, to generate highly accurate analog output signals with reduced complexity and cost, eliminating the need for an interpolation amplifier and minimizing calibration memory and time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional DAC circuits use more switches and resistor elements to achieve higher bit accuracy, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the DAC circuit into multiple segments: an R-2R DAC segment for MSB conversion and a resistor ladder segment for ISB conversion. This segmentation allows each segment to use fewer components while achieving overall high accuracy when combined, resolving the contradiction between precision and complexity.
Solution Approach 2:
The patent implements a nested structure where the resistor ladder is integrated within the R-2R DAC architecture. The R-2R DAC generates an initial analog output that is then refined by the resistor ladder, creating a nested functional relationship that achieves high precision without proportionally increasing overall circuit complexity.
2Manufacturing precision
If conventional DAC circuits increase the number of switches and resistor elements for higher accuracy, then manufacturing precision is improved, but the number of components increases
Solution Approach 1:
By segmenting the DAC into R-2R and resistor ladder portions, the patent reduces the number of switches and resistors needed in each segment compared to a conventional single-architecture high-precision DAC. The R-2R segment handles MSB with fewer components, while the resistor ladder handles ISB with a compact structure.
Solution Approach 2:
The patent applies different architectural approaches to different bit significance levels: R-2R architecture for MSB and resistor ladder for ISB. This local quality differentiation optimizes component usage for each function, reducing total component count while maintaining high overall precision.
3Manufacturing precision
If conventional DAC circuits provide high bit accuracy, then manufacturing precision is improved, but calibration memory and calibration time increase
Solution Approach 1:
The segmented architecture allows calibration to be performed separately on the R-2R DAC portion and the resistor ladder portion. This segmentation reduces the calibration memory required compared to calibrating a single high-precision DAC, and enables parallel or sequential calibration processes that reduce total calibration time.
Data Source
AI summary
A integrated circuit device includes digital-to-analog converter (DAC) circuitry including a resistor DAC that includes a resistor-two-resistor DAC configured to receive a first sub-word that includes a most significant bit (MSB) of a digital input signal and to output an analog output signal representative of the first sub-word, a resistor ladder configured to receive the analog output signal and a second sub-word that includes an intermediate significant bit (ISB) of the digital input signal and to generate an analog interpolated signal. The resistor ladder includes a plurality of resistor elements connected in series with one another to define a plurality of tap nodes, wherein a respective tap node is arranged between every two adjacent ones of the resistor elements, and a switching circuit having plurality of switches, wherein each switch is configured to selectively connect a respective one of the tap nodes to an output of the resistor ladder to generate the analog interpolated signal.