Quadruple-Speed Display via Segmented Interpolation Timing
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Solution Overview
Problem
The development of image interpolation chips that output high-speed image signals is time and cost-intensive due to the need for increased complexity and number of interpolated frames, which hinders the enhancement of display quality in display devices.
Innovation Solution
A display device architecture that utilizes two image interpolation chips and timing units to generate quadruple-speed image signals by inserting and correcting ¼-th, ½-th, and ¾-th interpolated frames between original frames, allowing for improved display quality without the need for extensive hardware upgrades.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an image interpolation chip outputs a high-speed image signal with an increased number of interpolated frames, then display quality is enhanced, but development time and costs are substantially increased
Solution Approach 1:
The patent divides the display panel into first and second display regions, and uses separate timing units (first and second timing units) to process image signals for each region. This segmentation allows parallel processing of different frame data, enabling quadruple-speed output without requiring a single complex high-speed interpolation chip, thus reducing development time and cost while maintaining high display quality
Solution Approach 2:
The patent combines the functionality of multiple image interpolation chips by using two image interpolation chips that each output low-speed image signals with interpolated frames, and then uses timing units to merge and retime these signals to achieve quadruple-speed output. This merging approach allows achieving high-speed output without developing a single complex high-speed interpolation chip
2Manufacturing precision
If an image interpolation chip outputs a high-speed image signal with an increased number of interpolated frames, then display quality is enhanced, but hardware complexity and costs are increased
Solution Approach 1:
The patent segments the image signal processing into multiple independent timing units, each handling specific frame data (e.g., first timing unit handles previous (n-1)-th frame and one interpolated frame, second timing unit handles other interpolated frames). This segmentation distributes hardware complexity across multiple simpler units rather than concentrating it in a single high-speed chip
Solution Approach 2:
The timing units act as intermediary components between the image interpolation chips and the display panel. They receive low-speed image signals with interpolated frames, correct gray levels, rearrange frame sequences, and output quadruple-speed signals. These intermediaries enable high-speed output without requiring the image interpolation chips themselves to operate at high speeds, thus reducing overall hardware complexity
Data Source
AI summary
A display device includes a display panel having pixels and divided into first and second display regions; first and second image interpolation chips which receive an original image signal and output interpolated ¼, ½, and/or ¾ frames inserted between a previous (n−1)-th frame and a current n-th frame of the original image signal; a first timing unit which receives the interpolated ¼, ½, and/or ¾ frames from the first image interpolation chip and outputs a first quadruple-speed image signal to pixels in the first display region; and a second timing unit which receives the interpolated ¼, ½, and/or ¾ frames from the second image interpolation chip and outputs a second quadruple-speed image signal to pixels in the second display region. The first timing unit transmits data to the second timing unit, and the second timing unit transmits data to the first timing unit.