Multi-Die IC Stress Reduction via Segmented Interposers

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Solution Overview

Problem

Multi-die integrated circuits face reliability issues due to high stress on interposers and connections, which can lead to defects and increased production costs, as the large size of interposers induces significant stress on solder bumps and other IC structures.

Innovation Solution

The use of multiple smaller interposers instead of a single monolithic interposer reduces stress on both the interposers and connected IC structures, with each interposer serving as a coplanar mounting surface and electrical coupling point for dies, and incorporating metal interconnects and TSVs for signal propagation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a single large interposer is used to mount multiple dies, then signal propagation between dies is enabled, but stress on solder bumps and interposer connections increases significantly

Engineering Contradiction:
Improvesignal propagation speedVSAvoidstress on solder bumps
Core Design Contradiction:
SpeedVSStress or pressure

Solution Approach 1:

The patent divides a single large interposer into multiple smaller interposers (first interposer, second interposer, etc.). Each interposer is mounted on the substrate and carries one or more dies. This segmentation reduces the stress on solder bumps and interposer connections while maintaining the ability to propagate signals between dies through the distributed interposer structure.

Inventive Principle:
Principle #1Segmentation

2Speed

If a single large interposer is used, then inter-die signal exchange is achieved, but reliability of connections decreases due to high stress

Engineering Contradiction:
Improveinter-die signal exchangeVSAvoidconnection reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

By segmenting the interposer structure into multiple smaller units, each interposer experiences reduced mechanical stress, thereby improving connection reliability. The multiple interposers work together to enable inter-die signal exchange, distributing the mechanical load while maintaining electrical connectivity.

Inventive Principle:
Principle #1Segmentation

3Stress or pressure

If multiple smaller interposers are used instead of a single large interposer, then stress on solder bumps is reduced, but device complexity increases

Engineering Contradiction:
Improvestress on solder bumpsVSAvoidinterposer structure complexity
Core Design Contradiction:
Stress or pressureVSDevice complexity

Solution Approach 1:

The patent applies segmentation by using multiple smaller interposers instead of one large interposer. While this increases the number of components, it significantly reduces stress on solder bumps and connections. The complexity is managed through systematic arrangement where each interposer is mounted on the substrate and carries specific dies, creating a modular and maintainable structure.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8704364B2Reducing stress in multi-die integrated circuit structures
Publication Date: 2014.04.22 XILINX INC
  • US8704364B2 patent drawing
  • US8704364B2 patent drawing
  • US8704364B2 patent drawing

AI summary

An integrated circuit structure can include a first interposer and a second interposer. The first interposer and the second interposer can be coplanar. The integrated circuit structure further can include at least a first die that is coupled to the first interposer and the second interposer.