Segmented Interposer Semiconductor Package for Multi-Chip Yield
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving high performance, compact size, and increased yield, particularly when multiple semiconductor chips are packaged together, as they struggle to efficiently connect and integrate multiple chips within a single package while maintaining manufacturing efficiency and reducing costs.
Innovation Solution
The semiconductor package design incorporates an interposer substrate with sub-interposers, a redistribution layer, and molding layers to electrically connect multiple semiconductor chips, allowing for horizontal spacing and efficient packaging, while the sub-interposers' areas are optimized to be less than the chip areas, enabling effective electrical connections and reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor chips are mounted in a single package with traditional interposer structures, then the packaging density and integration are improved, but the manufacturing complexity and cost increase
Solution Approach 1:
The interposer substrate is divided into multiple sub-interposers that are horizontally spaced apart from each other. Each sub-interposer includes through electrodes extending vertically through it. This segmentation allows independent processing and assembly of smaller interposer units, reducing overall manufacturing complexity while maintaining high packaging density through efficient space utilization.
Solution Approach 2:
The patent introduces a vertical dimension to the interposer structure by having through electrodes extend vertically through the sub-interposers. This three-dimensional electrode arrangement enables electrical connections in the vertical direction while keeping sub-interposers horizontally spaced, allowing high integration without proportionally increasing manufacturing complexity.
2Reliability
If the interposer substrate area is increased to accommodate multiple chips, then the electrical connection capability is improved, but the manufacturing cost and material usage increase
Solution Approach 1:
Instead of using a single large interposer substrate, the patent segments it into multiple smaller sub-interposers horizontally spaced apart. The sum of areas of these sub-interposers is less than the area of a single large interposer would be, reducing material usage while maintaining electrical connection capability through the distributed through electrodes in each sub-interposer.
Solution Approach 2:
The interposer substrate incorporates spaces between the horizontally spaced sub-interposers, creating a porous-like structure. These spaces reduce the total interposer material volume while the through electrodes in each sub-interposer ensure adequate electrical connection capability is maintained throughout the package.
3Volume of moving object
If the horizontal spacing between semiconductor chips is reduced for compact packaging, then the package size is decreased, but the manufacturing precision requirements increase
Solution Approach 1:
The sub-interposers with through electrodes act as intermediary structures between the semiconductor chips. The through electrodes extend vertically through the sub-interposers and provide robust electrical connection points, serving as mediators that facilitate precise alignment and connection even when chips are horizontally spaced closely together, thereby managing manufacturing precision requirements.
4Adaptability or versatility
If traditional single interposer structures are used, then the wiring freedom is limited, but the manufacturing process is simpler
Solution Approach 1:
The segmentation of the interposer into multiple sub-interposers with horizontally spaced arrangements and vertical through electrodes creates multiple independent wiring pathways. This segmented structure provides greater wiring freedom and adaptability for connecting multiple chips in various configurations, while each individual sub-interposer remains relatively simple to manufacture.
Solution Approach 2:
By adding the vertical dimension with through electrodes extending through the sub-interposers, the patent creates three-dimensional wiring pathways. This enables greater wiring freedom and adaptability for complex chip interconnections without proportionally increasing the complexity of each individual sub-interposer structure.
Data Source
AI summary
A semiconductor package includes a package substrate, an interposer substrate on the package substrate, first connection bumps between the package substrate and the interposer substrate, first and second semiconductor chips on the interposer substrate, second connection bumps between the interposer substrate and the first and second semiconductor chips, and an upper molding layer on the interposer substrate and at least partially surrounding the first semiconductor chip and the second semiconductor chip. The interposer substrate includes a plurality of sub-interposers horizontally spaced apart from each other and each including through electrodes, a lower molding layer in a space between the sub-interposers, and a redistribution layer electrically connected to the through electrodes on the sub-interposers and the lower molding layer. A sum of areas of the sub-interposers is less than a sum of areas of the first and second semiconductor chips.