Segmented Interposer Package for Multi-Chip Fine-Pitch Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing integration of semiconductor chips in electronic devices poses a challenge for printed circuit boards to accommodate the high degree of integration, leading to the need for a semiconductor package that can efficiently interconnect multiple chips while minimizing size and manufacturing costs.
Innovation Solution
A semiconductor package design that incorporates an interposer with a lower redistribution line structure, connection pillars, and an upper redistribution line structure, allowing for the interconnection of semiconductor chips without relying on a large interposer, thereby reducing manufacturing costs and maintaining high yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large interposer is used to interconnect multiple semiconductor chips, then the interconnection capability is improved, but the manufacturing cost increases and yield decreases
Solution Approach 1:
The patent divides the interconnection system into multiple small interposers instead of using one large interposer. Each small interposer has a footprint smaller than the semiconductor chips it supports, allowing standard manufacturing processes to be used while achieving the same overall interconnection capability through parallel arrangement of multiple units.
Solution Approach 2:
Multiple small interposers are arranged in a grid pattern where they collectively support and interconnect multiple semiconductor chips. The interposers are positioned such that their combined coverage area enables full interconnection without requiring any single interposer to be larger than the chips themselves.
2Adaptability or versatility
If a large interposer is used to interconnect multiple semiconductor chips, then the interconnection capability is improved, but the manufacturing yield decreases
Solution Approach 1:
By segmenting the interconnection function across multiple small interposers, the patent enables standard manufacturing processes with higher yield. Each small interposer can be manufactured independently with conventional techniques, avoiding the yield penalties associated with fabricating large, complex interposer structures.
Solution Approach 2:
The patent uses multiple identical or similar small interposer units that can be manufactured using the same standardized processes. This copying approach ensures consistent quality and high yield across all interposers, as each unit is produced under identical, optimized manufacturing conditions.
3Ease of manufacture
If printed circuit board is used for highly integrated semiconductor chips, then the manufacturing process is simple, but the integration capability is insufficient
Solution Approach 1:
The patent introduces small interposers as intermediary structures between the printed circuit board and highly integrated semiconductor chips. These interposers provide the necessary fine-pitch interconnection capability that PCBs cannot achieve alone, while still maintaining a relatively simple overall manufacturing process by combining standard PCB techniques with advanced interposer fabrication.
Data Source
AI summary
Provided is a semiconductor package including an interposer. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; at least one interposer including a plurality of first connection pillars spaced apart from each other on the lower redistribution line structure and connected respectively to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns connected respectively to the plurality of first connection pillars and the plurality of connection wiring patterns, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips adhered on the upper redistribution line structure while being spaced apart from each other.