Segmented I-O Chains for Reduced Pin-Count Testing
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Solution Overview
Problem
The increasing cost and pin requirements of automatic test equipment (ATE) for testing Input-Output (I-O) circuits in integrated circuits, which is becoming expensive due to large tester pin needs, while existing methods are not efficient in reducing test time and memory requirements.
Innovation Solution
A Self-Test and Repair I-O System (SIS) that includes on-chip components like I-Os, test processors, and soft wrappers, along with an external testing unit providing Parametric Measurement Unit (PMU) capability, allowing sequential access to I-Os for analog, timing, and digital data without causing routing congestion, using segmented I-O chains and reduced pin-count testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If automatic test equipment (ATE) is used to test I-O circuits, then testing capability and coverage are improved, but tester pin requirements and cost increase
Solution Approach 1:
The patent segments the I-O circuits into groups that can be tested sequentially through a small number of shared tester pins. The test processor on-chip coordinates sequential access to different I-O groups, allowing comprehensive testing with limited external pins. This segmentation approach enables testing of hundreds of I-Os using only a few tens of tester pins.
Solution Approach 2:
The patent introduces an on-chip test processor as an intermediary between the external ATE and the I-O circuits. This test processor manages test sequences, controls signal routing, and coordinates testing of multiple I-O groups sequentially. The intermediary enables the external tester to control complex on-chip test operations with minimal pin usage.
2Quantity of substance
If sequential access to I-Os is implemented, then pin count requirements are reduced, but test time may increase
Solution Approach 1:
The patent implements continuous testing by seamlessly transitioning between different I-O groups without idle time. The on-chip test processor maintains continuous test operation by preparing the next test group while previous groups are being tested, and by using dual-buffer architectures that allow overlapping of test preparation and execution phases.
Solution Approach 2:
The patent uses dynamic test group configuration where the composition and size of test groups can be adjusted based on I-O characteristics and test requirements. The system dynamically reconfigures which I-Os are tested in each group and optimizes the sequencing to minimize total test time while maintaining low pin count requirements.
3Quantity of substance
If more I-Os are tested with limited pins, then cost is reduced, but routing congestion may occur
Solution Approach 1:
The patent segments I-O circuits into spatially distributed groups that can be accessed through different on-chip signal paths. By dividing the I-O population into multiple segments with dedicated test access paths, the system avoids routing congestion while maintaining low external pin requirements. Each segment can be tested through its own internal routing structure.
Solution Approach 2:
The patent adds temporal dimension to the testing process by implementing time-multiplexed access to I-O groups. Instead of requiring simultaneous physical connections to all I-Os, the system uses time-division multiplexing where different I-O groups are accessed at different time slots through the same physical pin infrastructure, effectively adding a time dimension to resolve spatial routing constraints.
Data Source
AI summary
Various methods and apparatuses are described for a system that includes some on-chip components, e.g., I-Os, test processors, soft wrappers, etc., an external testing unit that provides Parametric Measurement Unit (PMU) capability, and various tests performed on the I-Os by the on-chip testing logic, the test vector patterns supplied by the external testing unit.