Segmented JTAG Boundary Scan Chain for Parallel IC Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing boundary scan chain testing methods for integrated circuit devices are time-intensive and inefficient, especially as integrated circuits become more complex and varied, leading to significant costs and resource challenges in testing diverse IO subsystems.
Innovation Solution
The implementation of modular JTAG boundary scan chain testing circuitry that allows for segmented testing of IO subsystems independently, using a JTAG network with multiplexers and Test Data Registers to route and output test signals efficiently across different types and numbers of IO subsystems, enabling parallel testing and reducing test pattern development resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional boundary scan chain testing is performed on all IO circuits of an integrated circuit device, then complete testing coverage is achieved, but testing time becomes excessively long and resource-intensive
Solution Approach 1:
The boundary scan chain is divided into multiple independent segments, each corresponding to a specific IO subsystem. Each segment can be tested independently through separate test access ports, allowing parallel testing execution. This segmentation maintains complete testing coverage across all IO circuits while significantly reducing total testing time by eliminating the need to sequentially test the entire boundary scan chain as a single unit.
2Reliability
If boundary scan chain testing is performed on all IO circuits, then comprehensive testing is achieved, but device complexity and test pattern development resources increase significantly
Solution Approach 1:
The test system is segmented into multiple independent testing modules, each responsible for a specific IO subsystem. This modular approach reduces overall system complexity by allowing each segment to be designed, implemented, and maintained independently, while still achieving comprehensive testing coverage when all segments are executed.
Solution Approach 2:
Each IO subsystem is equipped with its own boundary scan chain segment that can function independently. This multi-functionality allows the same testing infrastructure to be applied uniformly across different IO subsystems, reducing the need for specialized test patterns for each subsystem and thereby reducing overall test system complexity.
3Ease of manufacture
If traditional serial boundary scan chain testing is used across multiple integrated circuit dies, then testing is simplified, but productivity and testing throughput remain low
Solution Approach 1:
The boundary scan chain across multiple dies is segmented into parallel testing paths, with each die or group of dies having its own independent test access port and boundary scan chain segment. This allows multiple dies to be tested simultaneously in parallel rather than sequentially, dramatically increasing testing throughput while maintaining the simplicity of the boundary scan testing methodology.
Solution Approach 2:
Multiple independent boundary scan chain segments from different dies or IO subsystems are merged into a unified parallel testing framework. This combining of parallel testing capabilities maintains the ease of manufacture by using standard boundary scan techniques while achieving high productivity through concurrent execution of multiple test sequences.
Data Source
AI summary
Integrated circuit devices, methods, and circuitry for performing boundary scan chain testing is provided. Such an integrated circuit device may include a Joint Test Action Group (JTAG) network, a first input/output (IO) subsystem, and a second IO subsystem. The first IO subsystem includes first segmented boundary scan chain circuitry that can receive JTAG Test Data In (TDI) signals from a main JTAG test access port (TAP) of the JTAG network and use the JTAG TDI signals to perform a first boundary scan chain test. The second IO subsystem includes second segmented boundary scan chain circuitry that can receive the JTAG TDI signals from the main JTAG TAP of the JTAG network and use the JTAG TDI signals to perform a second boundary scan chain test in parallel with the first boundary scan chain test.


