Segmented Logical-to-Physical Mapping Tables for Lower DRAM Use
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Solution Overview
Problem
Conventional memory sub-systems face challenges in managing the increasing size of NAND memory, leading to excessive DRAM requirements and performance impacts due to write amplification, especially with larger NAND sizes, which affect endurance and performance.
Innovation Solution
Implementing a reduced-size logical-to-physical mapping table by storing block numbers and page table indices, reducing each entry's size and optimizing page table searches to maintain performance and minimize DRAM usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional full-size logical-to-physical mapping tables are used to manage large NAND memory, then complete address mapping is achieved, but DRAM size requirements increase excessively
Solution Approach 1:
The mapping table is segmented into multiple levels: a smaller first level mapping table stores frequently accessed mappings, while a second level mapping table stores less frequently accessed mappings. This hierarchical segmentation reduces the size of the primary mapping table that must reside in DRAM, thereby reducing DRAM size requirements while maintaining complete address mapping capability through the multi-level structure.
Solution Approach 2:
Different regions of the mapping table are assigned different qualities based on access frequency. Hot mappings (frequently accessed) are kept in the first level mapping table with smaller size for fast access, while cold mappings (less frequently accessed) are placed in the second level mapping table. This local differentiation optimizes the balance between mapping completeness and DRAM size by placing only essential mappings in the limited DRAM space.
2Quantity of substance
If larger NAND memory sizes are used to increase storage capacity, then storage capacity is improved, but write amplification increases and affects performance
Solution Approach 1:
The system performs preliminary actions by pre-fetching and caching mapping information in the first level mapping table before actual memory access operations occur. This allows frequently accessed mappings to be resolved quickly without requiring full traversal of the second level mapping table, thereby reducing write amplification and improving write performance even as storage capacity increases.
3Quantity of substance
If larger NAND memory sizes are used to increase storage capacity, then storage capacity is improved, but endurance decreases due to write amplification
Solution Approach 1:
The multi-level mapping table structure segments the address translation process, allowing the system to handle large storage capacities without proportionally increasing write amplification. By resolving common mappings at the first level with smaller overhead, the system reduces the total write operations required, thereby improving endurance while maintaining large storage capacity.
Data Source
AI summary
A logical-to-physical (L2P) data structure comprising a plurality of L2P table entries is maintained on the volatile memory device. Each L2P table entry comprises a block number and a page table index corresponding to the non-volatile memory device. A plurality of physical-to-logical (P2L) data structures each comprising a plurality of P2L table entries is maintained on the volatile memory device. Each of the plurality of P2L data structures corresponds to a portion of the L2P data structure.