Segmented LDMOS Gate Oxide for Low RxQg
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Solution Overview
Problem
Current power transistors, specifically laterally diffused metal oxide semiconductor (LDMOS) devices, face challenges in achieving a low gate voltage switch for high voltage loads due to fixed power device figure of merit (RxQg), which limits switching frequency and power efficiency, requiring costly technology changes.
Innovation Solution
The solution involves segmenting the gate oxide area of LDMOS transistors to reduce the total gate area over the thin gate dielectric, thereby reducing gate charge and channel resistance, improving the RxQg figure of merit through a simple layout change without requiring new process developments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the gate oxide area is reduced to reduce gate charge, then the RxQg figure of merit improves, but the channel width decreases leading to increased channel resistance
Solution Approach 1:
The gate oxide is divided into multiple segments separated by deep trenches filled with dielectric material. This segmentation reduces the total gate oxide area and gate charge while the deep trenches provide isolation that maintains channel performance by preventing unwanted interactions between adjacent gate segments.
Solution Approach 2:
The gate structure is made non-uniform by introducing alternating regions of wider and narrower spacing to the body region, creating local variations in electric field distribution. This allows optimization of charge control in high-field regions while maintaining adequate channel width in other regions, thereby reducing gate charge without excessively increasing channel resistance.
2Loss of energy
If technology changes are implemented to improve RxQg, then power device performance improves, but manufacturing cost increases
Solution Approach 1:
The gate oxide segmentation can be implemented using standard photolithography and etching processes that are already part of conventional LDMOS manufacturing. The deep trenches are formed using existing trench isolation techniques, allowing performance improvement without requiring new or expensive manufacturing technology.
Solution Approach 2:
The invention modifies geometric parameters (gate oxide area, trench depth, spacing dimensions) rather than requiring changes in material composition or fundamental process technology. These parameter adjustments can be made within the existing process capability window, avoiding costly technology transitions while achieving improved RxQg.
3Loss of energy
If the gate voltage is reduced for low voltage switching, then power efficiency improves, but the ability to switch high voltage loads is limited
Solution Approach 1:
The alternating spacing regions create localized high-field zones that enhance charge control efficiency, allowing the transistor to achieve full enhancement mode operation at lower gate voltages. The non-uniform gate structure optimizes the electric field distribution to maintain high voltage blocking capability while reducing the gate voltage required for switching.
Solution Approach 2:
The deep trenches introduce a vertical dimension to the gate structure, creating a three-dimensional field distribution that improves charge control. This vertical isolation allows better control of the depletion regions, enabling low voltage switching while maintaining high voltage load capability through enhanced field management.
Data Source
AI summary
A power transistor is provided with at least one transistor finger that lies within a semiconductor material. The gate oxide is segmented into a set of segments with thick field oxide between each segment in order to reduce gate capacitance and thereby improve a resistance times gate charge figure of merit.