Segmented LDMOS Gate Structure for Lower Miller Capacitance
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Solution Overview
Problem
Conventional LDMOS devices with field plate structures face challenges in high-frequency applications due to increased parasitic feedback capacitance, which degrades high-frequency performance and results in power loss, necessitating a reduction in gate-to-drain capacitance without compromising breakdown voltage and on-resistance.
Innovation Solution
The implementation of a gate structure divided into multiple segments with adjustable spacing, using standard CMOS fabrication technology, to reduce parasitic capacitance by minimizing the overlap area between the gate and drain/drift regions, thereby enhancing high-frequency performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a field plate structure is used to increase breakdown voltage and reduce on-resistance, then power performance is improved, but parasitic feedback capacitance (Miller capacitance) increases, degrading high-frequency performance
Solution Approach 1:
The gate structure is divided into multiple gate segments separated by insulating layers, which reduces the continuous overlap area between gate and drain, thereby reducing parasitic feedback capacitance while maintaining the field plate's voltage enhancement function
Solution Approach 2:
The gate structure uses different configurations in different regions: a first gate segment over the body region and second gate segments over the drift region, allowing localized optimization of electric field distribution and capacitance reduction
2Area of stationary object
If gate segments are spaced closer together, then device area is reduced, but parasitic capacitance increases due to greater overlap
Solution Approach 1:
Insulating layers are introduced as intermediary elements between adjacent gate segments, enabling spatial separation that reduces capacitive coupling while maintaining compact device layout
Solution Approach 2:
The gate structure combines conductive gate materials with insulating separation layers to create a composite structure that simultaneously achieves capacitance reduction and area efficiency
3Ease of manufacture
If the gate structure is simplified to reduce manufacturing complexity, then fabrication ease is improved, but control over parasitic capacitance and performance optimization are degraded
Solution Approach 1:
The gate is segmented into multiple sections that can be formed using standard photolithography and deposition processes, maintaining compatibility with existing CMOS fabrication while enabling precise control of overlap areas and parasitic capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces on-state resistance, parasitic capacitance, and switching loss, while maintaining breakdown voltage, thereby improving high-frequency performance and compatibility with standard CMOS processes.
Implementation Method 1
the added overlap between the gate and drift region of the device introduces undesirable parasitic feedback capacitance, also referred to as Miller capacitance, from drain to gate (Cgd)
Implementation Method 2
the field plate structure in a conventional MOSFET device helps to improve some device performance metrics (e.g., increasing the breakdown voltage of the device by modulating the electric field locally)
Implementation Method 3
The large gate polysilicon area also helps to accumulate electrons in the drift region under the field plate during an on-state of the LDMOS device, thereby reducing on-resistance (RDson) in the device
Data Source
AI summary
A high-frequency LDMOS device includes a semiconductor substrate of a first conductivity type, a doped drift region of a second conductivity type formed on the substrate, and a body region of the first conductivity type formed in the doped drift region. Source and drain regions of the second conductivity type are formed proximate an upper surface of the body region and doped drift region, respectively, and spaced laterally from one another. A first insulating layer is formed on the body and doped drift regions. A gate structure including multiple gate segments is formed on the first insulating layer. Each of the gate segments is spaced laterally from one another by a second insulating layer disposed between adjacent gate segments. A spacing between adjacent gate segments is controlled as a function of a thickness of the second insulating layer, a thickness of the first and second insulating layers being independently controlled.