Segmented LDO Regulator Control for Low Ripple DRAM Power
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Solution Overview
Problem
Current low-dropout regulators (LDOs) face challenges in reducing output ripple and power consumption, particularly in dynamic random-access memory (DRAM) applications where input voltage is low and operating frequency is high, leading to increased power consumption and output ripple due to frequent switching of power transistors.
Innovation Solution
A low-dropout regulator design utilizing three comparators and hysteresis controllers to control power transistors, with a slew rate limiter, which reduces the number of frequently switching power transistors and minimizes power consumption by segmenting power transistor control based on loading currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the switching slew rate of the power transistors is increased to provide larger current in shorter time, then the response speed and output capability are improved, but the output voltage ripple increases and the comparator power consumption increases
Solution Approach 1:
The patent segments the power transistor control into multiple stages using three comparators (first, second, and third comparators) that generate separate comparison signals. Each comparator controls a specific power transistor (first, second, or third power transistor) with different switching thresholds, dividing the load current regulation into distinct segments. This segmentation allows controlled switching of individual transistors rather than all transistors switching simultaneously, reducing output voltage ripple while maintaining fast response capability.
2Stability of the object's composition
If the power transistors switch frequently to maintain output voltage under varying load conditions, then the output voltage stability is improved, but the power consumption of the comparator increases
Solution Approach 1:
The patent divides the voltage regulation task among three comparators, each monitoring different voltage thresholds (first, second, and third reference voltages). Each comparator only activates when its specific threshold condition is met, segmenting the monitoring workload. This allows the system to maintain output voltage stability through distributed comparison operations rather than all comparators continuously operating, thereby reducing overall comparator power consumption.
Solution Approach 2:
The patent employs different reference voltage levels (first reference voltage higher than second reference voltage, which is higher than third reference voltage) to create staged switching thresholds. By changing the voltage parameters at which each comparator triggers, the system optimizes the switching frequency of each power transistor, reducing unnecessary frequent switching and thereby lowering comparator power consumption while maintaining stability.
3Use of energy by moving object
If the input voltage is reduced to meet lower power requirements, then the power efficiency is improved, but the available voltage headroom for regulation is reduced
Solution Approach 1:
The patent segments the voltage regulation process into three distinct stages using multiple comparators with different reference voltages. This staged approach allows the system to operate effectively with reduced input voltage by activating only the necessary power transistors based on current load conditions, maximizing the utilization of available voltage headroom while maintaining regulation capability.
Solution Approach 2:
The patent implements dynamic control of power transistors through multiple comparators that continuously monitor output voltage and adjust transistor switching states in real-time. This dynamic adaptation allows the system to optimize performance across varying input voltage conditions, maintaining voltage regulation headroom even when input voltage is reduced for improved power efficiency.
Data Source
AI summary
A low-dropout regulator including a first comparator, an edge trigger, a second comparator, a third comparator, and an output stage circuit is provided. The first comparator generates a first comparison signal according to a first reference signal and an output signal. The edge trigger outputs a trigger signal according to the first comparison signal, a second comparison signal, and a third comparison signal. The second comparator generates the second comparison signal according to the output signal and a second reference signal. The third comparator generates the third comparison signal according to the output signal and a third reference signal. The output stage circuit outputs the output signal according to the first comparison signal, the second comparison signal, and the third comparison signal. The output stage circuit includes a plurality of hysteresis controllers and a plurality of power transistors. Each hysteresis controller controls a conduction state of a corresponding power transistor.