Segmented LDPC Interleaving for High-Order Modulation Mapping
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Solution Overview
Problem
In communication and broadcasting systems, high digital communication systems face challenges due to noise, fading, and inter-symbol interference, which affect data throughput and reliability, particularly in next-generation mobile communication and digital broadcasting. The performance of Low Density Parity Check (LDPC) codes is hindered by the complexity of mapping codeword bits onto high-order modulation bits.
Innovation Solution
A transmitting apparatus and method that includes an encoder for generating LDPC codewords, an interleaver to rearrange these codewords, and a modulator to map the interleaved LDPC codewords onto modulation symbols using a block interleaver. The interleaver divides columns into two parts, ensuring that bit groups are written in a specific pattern across multiple columns to enhance the mapping process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If LDPC codeword bits are mapped onto high order modulation bits, then data throughput is improved, but mapping complexity increases
Solution Approach 1:
The interleaver is divided into multiple columns, with each column further segmented into a first part and a second part. This segmentation allows systematic organization of bit groups during interleaving, simplifying the mapping process while maintaining high data throughput capability.
Solution Approach 2:
The block interleaver performs preliminary interleaving of LDPC codeword bits before modulation mapping. By pre-organizing bits into columns and parts with specific writing patterns, the system prepares the data structure in advance, reducing the complexity of the subsequent mapping operation onto high-order modulation symbols.
2Reliability
If iterative decoding based on sum-product algorithm is applied, then decoding performance approaches channel capacity, but computational complexity increases
Solution Approach 1:
The LDPC code structure is organized with systematic segmentation into bit groups and column partitions. This structured segmentation facilitates efficient iterative decoding by organizing the computation into manageable units, reducing overall computational complexity while maintaining near-capacity performance.
3Manufacturing precision
If block interleaver divides columns into first part and second part, then bit group mapping is improved, but interleaver structure complexity increases
Solution Approach 1:
Each column of the block interleaver is segmented into a first part and a second part, enabling precise control over bit group placement. This segmentation allows different writing patterns for different parts, improving mapping precision while keeping the structural complexity manageable through systematic organization.
Solution Approach 2:
Different parts of the interleaver columns have different properties: the first part uses one writing pattern while the second part uses another. This local differentiation optimizes bit group mapping for specific requirements in each region, achieving high mapping precision without requiring complete redesign of the entire interleaver structure.
Data Source
AI summary
A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver is formed of a plurality of columns including a plurality of rows, respectively, and comprises: a block interleaver configured to divide each of the plurality of columns into a first part and a second part, and interleave a plurality of bit groups constituting the LDPC codeword, all bit groups interleaved by the first part are interleaved as bits included in a same bit group are written in a same column of the first part, at least one bit group interleaved by the second part is interleaved as bits included in the at least one bit group are divided and written in at least two columns constituting the second part.