Multi-Way Tree Cache Management Using Segmented LRU Lists

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Traditional LRU linked lists used for caching in multi-way trees do not consider the tree structure, leading to premature swapping out of important nodes like root and intermediate nodes, causing bottlenecks and reduced system performance due to frequent operations.

Innovation Solution

Divide LRU linked lists into multiple lists based on tree levels, prioritizing nodes by their importance and reducing frequent operations by deleting accessed nodes from the list.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single LRU linked list is used to cache nodes in memory, then memory management is simple, but important nodes like root and intermediate nodes are swapped out prematurely causing frequent re-operations and system performance degradation

Engineering Contradiction:
Improvecache management structureVSAvoidsystem performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent divides the single LRU linked list into multiple separate LRU linked lists, with each list corresponding to a specific level of the multi-way tree (root level, intermediate level, leaf level). This segmentation allows different caching strategies to be applied to different node types, preventing important root and intermediate nodes from being swapped out prematurely while maintaining manageable complexity through structured organization.

Inventive Principle:
Principle #1Segmentation

2Speed

If nodes are cached in memory using traditional LRU algorithm, then access speed is improved, but memory pressure increases causing frequent swap operations

Engineering Contradiction:
Improvenode access speedVSAvoidmemory usage
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent applies different caching policies to different levels of the multi-way tree. Root nodes and intermediate nodes, which are more important for system operation, are cached with higher priority in dedicated LRU lists. This local differentiation of caching quality allows critical nodes to remain in memory longer, improving access speed for important operations while managing overall memory pressure through level-specific control.

Inventive Principle:
Principle #3Local quality

3Quantity of substance

If frequent swap operations are performed to manage memory, then memory pressure is reduced, but system performance deteriorates due to bottlenecks

Engineering Contradiction:
Improvememory capacity availabilityVSAvoidsystem throughput
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

By segmenting the cache into multiple level-specific LRU lists, the patent reduces the frequency of swap operations for important nodes. Root and intermediate nodes have their own dedicated lists that prevent them from being swapped out during memory pressure events, thereby maintaining system throughput while still managing memory capacity through controlled swapping of less critical leaf nodes.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10698831B2Method and apparatus for data access
Publication Date: 2020.06.30 EMC IP HLDG CO LLC
  • US10698831B2 patent drawing
  • US10698831B2 patent drawing
  • US10698831B2 patent drawing

AI summary

Embodiments of the present disclosure relates to a method and device of data access. The method comprises determining whether target data stored in a non-volatile storage device is cached in a memory. The target data is organized in a first level of a multi-way tree in the storage device. The method further comprises, in response to determining that the target data is missing in the memory, moving the target data from the storage device into the memory. Besides, the method comprises, in response to the target data being accessed from the memory, adding a reference to the target data to a first list, the first list recording a sequence for accessing data in the first level.