Segmented Memory Access Lines Mitigating Discharge Current Spikes

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Solution Overview

Problem

Current memory arrays face damage from current spikes due to internal discharge, which can degrade or wear out memory cells, especially those near access line drivers, as built-up charge discharges through selected cells, causing high current spikes.

Innovation Solution

The access lines in memory arrays are segmented, with each segment coupled to the access line driver via separate vias, increasing the signal path length and resistance, thereby reducing the magnitude of current spikes through memory cells by dissipating charge more slowly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If access lines are segmented with separate vias to increase signal path length and resistance, then current spike magnitude is reduced and memory cell lifespan is extended, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvememory cell lifespanVSAvoidaccess line structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The access lines are divided into multiple segments with discontinuous structures, where each segment is separated by gaps and connected through separate vias to the driver. This segmentation increases the signal path length and resistance, thereby reducing current spike magnitude and protecting memory cells from degradation while maintaining functional integrity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Separate vias are introduced as intermediary elements between the segmented access lines and the driver. These vias act as mediators that increase the discharge path length and resistance, effectively reducing current spike magnitude without directly modifying the memory cell structure

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If access lines are segmented to dissipate charge more slowly, then current spikes are mitigated, but signal transmission speed may be reduced

Engineering Contradiction:
Improvecurrent spike magnitudeVSAvoidsignal transmission speed
Core Design Contradiction:
Object-affected harmful factorsVSSpeed

Solution Approach 1:

The segmentation and via structure are applied specifically to access lines that are prone to high current spikes, such as those near drivers or in specific regions of the memory array. This localized application allows charge dissipation control where needed without unnecessarily slowing down signal transmission in other regions

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The access lines are partially segmented rather than completely discontinuous, with strategic gaps and via connections that provide sufficient resistance to reduce current spikes while maintaining adequate signal transmission speed for normal operation

Inventive Principle:
Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration mitigates current spikes, extending the lifespan of memory cells and reducing the risk of damage by distributing the discharge through a longer, more resistive path, thus protecting memory cells from degradation.

Implementation Method 1

increasing the signal path length and resistance, thereby reducing the magnitude of current spikes through memory cells by dissipating charge more slowly

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS11417375B2Discharge current mitigation in a memory array
Publication Date: 2022.08.16 MICRON TECHNOLOGY INC
  • US11417375B2 patent drawing
  • US11417375B2 patent drawing
  • US11417375B2 patent drawing

AI summary

Methods, systems, and devices for discharge current mitigation in a memory array are described. Access lines of a memory array may be divided into discrete segments, with each segment coupled with a driver for the access line by one or more vias respective to the segment. For example, a first segment of an access line may be coupled with a first set of memory cells, a second segment of the access line may be coupled with a second set of memory cells, and a driver may be coupled to the first segment by a first via and to the second segment by a second via. To access a memory cell in either the first set or the second, both the first segment of the access line and the second segment of the access line may be activated together by the common driver.