Segmented Memory Circuit Layout for Lower Access Time and Power
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Solution Overview
Problem
The increase in power consumption and access time in memory circuits due to larger frame sizes and longer bus interconnects in semiconductor devices processing video data is a challenge.
Innovation Solution
A memory circuit design with multiple memory groups and controllers that control access signals to minimize long-distance routing of command and data lines, using flip-flops and repeater circuits to synchronize operations across groups, and implementing power-saving modes to reduce power consumption while maintaining access efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory capacity is increased to store larger video data frames, then the memory capacity increases, but the access time increases and power consumption increases
Solution Approach 1:
The memory circuit is divided into multiple independent memory groups (MG0-MG7), each with its own controller. This segmentation allows parallel access to different memory groups, reducing the overall access time even as total memory capacity increases. The hierarchical structure with first and second memory controllers enabling simultaneous operations on different groups resolves the contradiction between increased capacity and maintained access speed.
2Quantity of substance
If the memory capacity is increased to store larger video data frames, then the memory capacity increases, but the power consumption increases
Solution Approach 1:
The memory system is segmented into multiple groups that can be independently controlled and powered. Only the memory groups currently being accessed need to be in high-power mode, while other groups can remain in low-power mode. This segmentation enables selective power management, allowing large total memory capacity while consuming power only when needed for specific groups.
Solution Approach 2:
The memory groups can dynamically switch between low-power mode and normal mode based on access requirements. The control logic activates only the necessary memory groups, enabling the system to maintain large memory capacity while adapting power consumption to actual usage patterns, thus resolving the contradiction between capacity and power consumption.
3Quantity of substance
If the bus interconnects are made longer to connect all memory groups, then the memory capacity increases, but the access time increases
Solution Approach 1:
The memory system is segmented into multiple groups with distributed controllers, eliminating the need for a single long bus interconnect. Each memory group has local control logic, reducing the interconnect length to only span adjacent groups. This segmentation maintains short connection paths even as total memory capacity expands across multiple groups.
Solution Approach 2:
The memory groups are arranged in a hierarchical structure with multiple levels of controllers (first and second memory controllers). This dimensional organization allows data to be accessed through shorter local paths within groups rather than requiring long interconnects across the entire memory array, resolving the contradiction between expanded capacity and interconnect length.
Data Source
AI summary
A memory circuit includes memory groups each of which includes memory cells, and is configured to execute a write operation or a read operation in response to a request signal; memory group controllers each of which is provided for a corresponding one of the memory groups; and a first memory controller configured to output a request signal received from an outside to an adjacent memory group controller, wherein, in a case where an address signal included in the received request signal indicates the corresponding one of the memory groups, said each of the memory group controllers outputs the request signal to the corresponding one of the memory groups, and in a case where the address signal indicates a memory group other than the corresponding one of the memory groups, outputs the request signal to a memory group controller at a succeeding stage.