Segmented Memory Array Layout for Accurate High-Density Reads
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Solution Overview
Problem
Current memory devices face challenges in increasing memory capacity per unit area while maintaining data accuracy and reducing error incidence, particularly due to increased parasitic capacitance and resistance as the number of memory cells grows, leading to issues with data retention and read accuracy.
Innovation Solution
The memory device employs a structure with divided bit lines and word lines, controlled by multiple driver circuits, and uses transistors with oxide semiconductors for low off-state current and high mobility, allowing for reduced parasitic capacitance and resistance, and a three-dimensional overlap of driver circuits and cell arrays to minimize area occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells is increased to achieve large storage capacity, then memory capacity per unit area is improved, but parasitic capacitance and resistance of bit lines and word lines are increased, leading to reduced data read accuracy
Solution Approach 1:
The memory device is divided into a plurality of memory blocks, where each block contains a subset of memory cells connected to dedicated bit lines and word lines. This segmentation limits the number of memory cells per bit line and per word line, thereby reducing parasitic capacitance and resistance in each signal path while maintaining high overall memory capacity through parallel block structure.
2Area of stationary object
If the area of capacitor is reduced to decrease memory cell area, then memory capacity per unit area is improved, but difference between amounts of electric charge corresponding to different digital values becomes smaller, making it difficult to maintain data accuracy
Solution Approach 1:
By dividing the memory into multiple blocks with dedicated bit lines and word lines for each block, the parasitic capacitance and resistance affecting charge detection are minimized. This allows for smaller capacitor areas while maintaining sufficient charge difference detection accuracy through reduced signal degradation in the read path.
3Device complexity
If the number of memory cells connected to one bit line is increased to reduce bit line quantity, then device complexity is reduced, but parasitic capacitance and resistance of bit line are increased, leading to reduced data read accuracy
Solution Approach 1:
The memory cells are organized into multiple blocks, with each block having its own dedicated bit lines and word lines. This segmentation increases the total number of bit lines and word lines but limits the number of memory cells connected to each individual bit line and word line, thereby reducing parasitic capacitance and resistance in each signal path while maintaining manageable device complexity through systematic organization.
4Measurement precision
If the distance of bit line is reduced to decrease parasitic capacitance and resistance, then data read accuracy is improved, but memory cell area increases, reducing memory capacity per unit area
Solution Approach 1:
The memory is divided into multiple compact blocks distributed across the substrate. Each block contains memory cells connected to relatively short bit lines and word lines, minimizing parasitic capacitance and resistance. The overall memory capacity is achieved through the parallel arrangement of multiple blocks rather than extending single long bit lines across large distances.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased memory capacity per unit area, improved data retention, reduced error incidence, and enhanced reliability by minimizing parasitic effects and optimizing layout, thus supporting higher integration and performance.
Implementation Method 1
Transistors in each of which a channel formation region is formed using such a metal oxide having semiconductor characteristics have been known
Data Source
AI summary
An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.