Segmented Memory Arrays with Variable Capping Materials
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Solution Overview
Problem
The integration of different types of memory devices in System-On-Chip (SOC) technology is complex due to varying memory performance requirements, making it difficult to design and manufacture integrated circuits that efficiently address these needs.
Innovation Solution
The use of first and second pluralities of memory cells with different capping materials, such as silicon nitride, to apply distinct write processes and allocate them for specific memory specifications, including higher speed programming and longer data retention, while maintaining a common cell structure and utilizing programmable resistance memory materials like GexSbyTez phase change materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different types of memory devices are integrated in SOC to address varying memory performance requirements, then memory performance requirements are met, but design and manufacturing complexity increases
Solution Approach 1:
The memory array is segmented into multiple regions, each with different capping materials (e.g., first region with capping material having first properties, second region with capping material having second properties). This segmentation allows each region to be optimized for specific memory performance requirements while maintaining a unified memory structure, thereby reducing design and manufacturing complexity compared to integrating entirely separate memory devices.
Solution Approach 2:
Different capping materials are applied to different regions of the memory array based on local performance requirements. For example, regions requiring high-speed access use capping materials with properties optimized for speed, while regions requiring long-term retention use capping materials optimized for retention. This local quality approach enables tailored performance optimization without increasing overall device complexity.
2Adaptability or versatility
If multiple memory types are integrated with different structures, then memory performance requirements are addressed, but manufacturing process complexity increases
Solution Approach 1:
The memory array structure is designed to be universal, accommodating multiple memory types within the same basic architecture. By varying only the capping material properties in different regions while maintaining the same fundamental memory cell structure, the design achieves multi-functionality without requiring separate manufacturing processes for different memory types, thereby simplifying manufacturing.
Solution Approach 2:
The invention achieves different memory types by changing material parameters (capping material composition, density, or properties) rather than changing the fundamental device structure. This parameter-based differentiation allows standard manufacturing processes to produce multiple memory types simultaneously, reducing manufacturing process complexity while still addressing diverse performance requirements.
3Productivity
If different write processes are applied to different memory regions, then programming speed and data retention are optimized, but control complexity increases
Solution Approach 1:
The capping materials are pre-configured in different regions according to the intended memory performance characteristics before the memory is put into operation. This preliminary action means that the optimization for programming speed or data retention is built into the physical structure itself, reducing the need for complex real-time control during write operations. The control complexity is minimized because the system leverages the inherent properties of the pre-configured capping materials rather than requiring complex dynamic adjustment mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of integrated circuits with memory arrays that achieve both high speed and long data retention, effectively addressing the complexity of integrating multiple memory types by optimizing the capping materials and write algorithms for each set of memory cells.
Implementation Method 1
The memory cells in the first and second pluralities of memory cells can have memory elements comprising a GexSbyTez phase change material
Data Source
AI summary
A device includes first and second pluralities of memory cells with memory elements and first and second capping materials on the first and second pluralities of memory cells. First and second capping materials can comprise lower and higher density silicon nitrides. The memory elements can include a programmable resistance memory material, and the capping materials can contact the memory elements. The first and second pluralities of memory cells can have a common cell structure. The first memory cells in the can comprise a top and bottom electrodes with a memory material therebetween and the first capping material contacting the memory material. Control circuits can apply different write algorithms to the first and second pluralities of memory cells. The first and second sets of memory cells can have different operational memory characteristics by forming the first and second capping layers using different capping materials but with the same cell structure.