Segmented Memory Macro Vertical Stacking Word Line Assertion
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Solution Overview
Problem
Conventional semiconductor memory devices with longer Word Lines (WLs) suffer from degraded speed and inefficient layout due to aspect ratio issues, leading to wasted area on chips, especially as memory devices increase in size.
Innovation Solution
The proposed solution involves splitting a conventional memory device into two segments arranged one over the other, with Bit Lines (BLs) from the top segment going over the bottom segment in an upper metal layer, allowing two Word Lines to be activated in one cycle, thereby reducing WL lengths and improving efficiency and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If Word Lines are made longer to increase memory device size, then memory capacity increases, but speed degrades and layout efficiency worsens
Solution Approach 1:
The memory device is divided into two segments arranged vertically, with each segment having its own Word Line. This segmentation allows the memory capacity to be doubled while keeping each Word Line length manageable, thus maintaining access speed despite increased capacity.
Solution Approach 2:
The patent transitions from a conventional horizontal expansion approach to a vertical stacking arrangement. By utilizing the vertical dimension (upper and lower metal layers), the memory device can increase capacity without proportionally increasing Word Line length, thereby preserving speed performance.
2Quantity of substance
If Word Lines are made longer to increase memory device size, then memory capacity increases, but layout efficiency and area utilization worsen
Solution Approach 1:
By segmenting the memory device into two vertically stacked sections, each with independent Word Lines, the layout can be optimized to use chip area more efficiently. This avoids the wasted area that occurs when long Word Lines are used in conventional single-layer designs.
Solution Approach 2:
The vertical stacking of memory segments utilizing upper and lower metal layers improves area utilization by effectively using the third dimension (vertical space) rather than only horizontal expansion, leading to better chip area efficiency.
3Speed
If Word Line length is reduced by splitting memory segments, then speed improves, but device complexity increases
Solution Approach 1:
The memory device is segmented into two independent sections with separate Word Lines, which reduces Word Line length and improves speed. The segmentation is structured in a systematic way that manages complexity through clear separation of functions and standardized interconnections.
Solution Approach 2:
The Bit Lines serve multiple functions by spanning across both upper and lower segments, allowing a single Bit Line structure to handle data access for both segments. This multi-functionality reduces overall device complexity despite the segmented architecture.
Data Source
AI summary
A memory macro system may be provided. The memory macro system may comprise a first segment, a second segment, a first WL, and a second WL. The first segment may comprise a first plurality of memory cells. The second segment may comprise a second plurality of memory cells. The first segment may be positioned over the second segment. The first WL may correspond to the first segment and the second WL may correspond to the second segment. The first WL and the second WL may be configured to be activated in one cycle.