Segmented Nonvolatile Memory Array With Mirrored Access

Solution Overview

Problem

Current non-volatile memory devices face challenges in achieving improved speed, reliability, and flexibility while maintaining smaller sizes for increased storage capacities, particularly in their array architectures.

Innovation Solution

A segmented memory device architecture is introduced, featuring non-linear access order and interleaved patterns, with decoders and lines configured to allow concurrent targeting of memory cells, including bit line and tunneling line decoders, and word line decoders, enabling efficient operation and error minimization through mirroring and hierarchical organization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a conventional linear array architecture is used, then the device structure is simple, but the operational speed and flexibility are limited

Engineering Contradiction:

Improveoperational speedVSAvoidarray architecture complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The memory array is divided into multiple segments (first segment, second segment, third segment, fourth segment) arranged in a non-linear configuration. Each segment can be accessed independently through dedicated decoders, allowing parallel operations and improving overall operational speed while managing complexity through modular organization.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from a conventional linear array layout to a multi-dimensional segmented architecture with non-linear access patterns. This dimensional reorganization allows concurrent access to multiple memory cells through different segments, significantly enhancing operational speed and flexibility.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If memory cells are accessed in linear order, then the decoder design is simple, but the reliability and error minimization are reduced

Engineering Contradiction:

Improveerror minimizationVSAvoiddecoder architecture complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The memory array is divided into multiple segments (first segment, second segment, third segment, fourth segment) arranged in a non-linear configuration. Each segment can be accessed independently through dedicated decoders, allowing parallel operations and improving overall operational speed while managing complexity through modular organization.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from a conventional linear array layout to a multi-dimensional segmented architecture with non-linear access patterns. This dimensional reorganization allows concurrent access to multiple memory cells through different segments, significantly enhancing operational speed and flexibility.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Productivity

If concurrent functional operations are enabled, then the productivity is improved, but the device complexity increases

Engineering Contradiction:

Improveconcurrent operation capabilityVSAvoidcontrol architecture complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The memory array is divided into multiple segments (first segment, second segment, third segment, fourth segment) arranged in a non-linear configuration. Each segment can be accessed independently through dedicated decoders, allowing parallel operations and improving overall operational speed while managing complexity through modular organization.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The segmented architecture with non-linear access patterns and multiple decoders enables the memory device to perform multiple functional operations (read, write, erase, verify) concurrently on different segments. This multi-functionality approach allows simultaneous execution of different operations, significantly enhancing productivity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8116110B1Array architecture including mirrored segments for nonvolatile memory device

Publication Date: 2012.02.14 MARVELL ASIA PTE LTD

AI summary

A memory device including nonvolatile memory cells arrayed in a first direction and in a second direction, a plurality of first lines extending in the first direction for coupling memory cells arrayed in the first direction, and a plurality of second lines extending in the second direction for coupling memory cells arrayed in the second direction. The memory device includes a plurality of decoders, including i) first decoders coupled to the first lines and ii) second decoders coupled to the second lines, for accessing any one or more of the memory cells in any order. The memory device includes a plurality of segments. Each segment includes different ones of the nonvolatile memory cells. A first one of the segments is juxtaposed to, in the second direction, a second one of the segments. The second one of the segments mirrors, in the second direction, the first one of the segments.