Data Packet Processing Device with Segmented Memory Architecture
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Solution Overview
Problem
Conventional packet-switched communication systems face bandwidth limitations and low access speed due to the use of external memory, which is accessed via an external interface, despite needing efficient storage management for varying PDU sizes and unpredictable traffic volumes.
Innovation Solution
A data processing device with a processor, on-chip internal segment memory, and off-chip external segment memory with multiple segment sizes, along with a data transfer channel and memory segment allocation management using internal and external table memories to optimize storage and access efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If external memory is used for storing PDUs, then storage capacity is sufficient for high traffic volume, but bandwidth limitations and low access speed occur
Solution Approach 1:
The patent divides the external memory into multiple segments of different sizes, where each segment can be independently allocated to different applications or protocols. This segmentation allows the system to optimize access patterns by directing time-critical data to smaller, faster-access segments while using larger segments for bulk storage, thereby improving overall access speed without sacrificing total storage capacity.
Solution Approach 2:
The patent implements a hybrid memory architecture where a small portion of memory (internal or dedicated external segment) is optimized for high-speed access with full bandwidth, while the majority of memory (external segments) provides large capacity at lower cost. This local quality differentiation allows the system to achieve both high access speed for critical operations and sufficient storage capacity for high traffic volumes.
2Speed
If internal memory is used for storing PDUs, then access speed is fast and tightly coupled to protocol processing, but storage capacity is insufficient for high traffic volume
Solution Approach 1:
The patent segments the memory system into internal and external portions, with the internal memory providing fast access for active protocol processing and external memory segments providing additional capacity for queued or less time-critical PDUs. This segmentation resolves the contradiction by allowing the system to use fast internal memory when speed is critical while offloading to external segments when capacity is needed.
Solution Approach 2:
The patent creates a nested memory hierarchy where internal memory is embedded within the protocol processor chip, and external memory segments are accessible through the external interface. This nesting allows the system to leverage both the speed of internal memory and the capacity of external memory, with the internal memory acting as a high-speed buffer nested within the larger external memory system.
3Ease of manufacture
If segment memories of fixed size are used, then efficient storage management is achieved, but flexibility in handling varying PDU sizes is limited
Solution Approach 1:
The patent divides the external memory into multiple segments of different sizes, where each segment can be independently allocated to different applications or protocols. This segmentation allows the system to optimize access patterns by directing time-critical data to smaller, faster-access segments while using larger segments for bulk storage, thereby improving overall access speed without sacrificing total storage capacity.
Solution Approach 2:
The patent implements dynamic segment allocation where memory segments can be freely allocated to different applications or protocols based on current traffic requirements. This dynamic allocation mechanism allows the system to adapt to varying PDU sizes and traffic patterns in real-time, providing both the efficiency of structured segment management and the flexibility needed for diverse communication protocols and variable data sizes.
Data Source
AI summary
A device for data packet processing is disclosed. In one embodiment, the device includes a processor implemented on a chip, an on-chip internal segment memory accessible by the processor, an off-chip external segment memory and a data transfer channel between the internal segment memory and the external segment memory. The external segment memory comprises first and second memory segments wherein the first and second memory segments are different in size.