Segmented In-Memory Compute Arrays for Parallel Independent Operations
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Solution Overview
Problem
Existing in-memory computation systems face challenges in efficiently performing multiple independent in-memory computation operations simultaneously due to limitations in data transfer bandwidth and power consumption.
Innovation Solution
The implementation of a segmented memory architecture with a matrix of local memory arrays allows for the simultaneous performance of multiple independent in-memory computation operations by selectively mapping local memory arrays to each operation and using a control circuit to generate row and column selection signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single memory array is used for in-memory computation, then the system structure is simple, but the system cannot perform multiple independent computation operations simultaneously and is limited by data transfer bandwidth
Solution Approach 1:
The memory array is divided into multiple independent local memory arrays (e.g., 16 local memory arrays arranged in a 4x4 matrix). Each local memory array can be independently selected and operated on, allowing multiple independent computation operations to be performed simultaneously on different local memory arrays without interfering with each other. This segmentation enables parallel processing while maintaining a relatively simple overall structure.
2Use of energy by moving object
If data is transferred frequently between memory device and computing device, then computation can be performed, but power consumption increases and data transfer bandwidth limitations are encountered
Solution Approach 1:
The system performs computation operations directly within the memory device using the stored data, eliminating the need for frequent data transfers between the memory device and computing device. The local memory arrays perform multiply-accumulate operations and other computations using their locally stored weights and input data, generating results that are then read out. This self-service approach significantly reduces power consumption associated with data transfer while maintaining high computation performance.
3Productivity
If multiple independent computation operations are performed simultaneously, then productivity increases, but the requirement for memory array selection and control increases
Solution Approach 1:
The control circuit is designed with universal functionality to manage multiple local memory arrays through standardized row select and column select signals. The same control circuit can selectively activate any combination of local memory arrays by controlling the row and column select lines, allowing flexible configuration for different computation operations without requiring dedicated control circuitry for each local memory array. This multi-functional control approach enables simultaneous operation of multiple local memory arrays while keeping the control circuit complexity manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient and simultaneous execution of multiple in-memory compute operations, reducing power consumption and overcoming data transfer bandwidth limitations, while maintaining independent output results.
Implementation Method 1
a PCM-type memory cell 14 is configured to store data using a phase change material (such as a chalcogenide) that is capable of stably transitioning between amorphous and crystalline phases according to an amount of heat transferred thereto
Implementation Method 2
The amorphous and crystalline phases exhibit two (in binary configuration) or more (in multi-ary configuration) distinct resistances corresponding to the variable resistive element 14r, in other words two or more distinct conductances
Data Source
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AI summary
An in-memory computation circuit, comprising: a memory including a plurality of memory cells arranged in a matrix with a plurality of cell rows and a plurality of cell columns, wherein each cell row is associated with a word line connected to the memory cells in the cell row, and wherein each cell column is associated with a global bit line, wherein the memory is segmented into a plurality of local memory arrays arranged in a matrix with a plurality of array rows and a plurality of array columns; a word line driver for each array row that is configured to be selectively enabled in response to a row select signal to drive word lines of the array row, wherein each local memory array includes a plurality of local bit lines connected to memory cells in the cell columns and a column decoder circuit configured to selectively connect the local bit lines to the global bit lines of the array column in response to a column select signal; and a control circuit configured to generate row select signals for the word lines drivers and column select signals for the column decoder circuits to map a first group of one or more local memory arrays to participate in a first in-memory compute operation producing computation output signals on first ones of the global bit lines and map a second group of one or more local memory arrays, different from the first ones of the local memory arrays, to participate in a second in-memory compute operation producing computation output signals on second ones of the global bit lines, different from the first ones of the global bit lines. The first and second in-memory compute operations are configured to be substantially simultaneously executed.