Segmented Memory Protection Reduces Soft Error Rate
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Solution Overview
Problem
Semiconductor memory systems face high soft error rates due to radiation and high-energy particles, leading to potential catastrophic failures, especially in internal processor memory where parity and ECC are not used, resulting in data loss and system instability, particularly in critical applications like telecommunications and medical/military equipment.
Innovation Solution
The internal processor memory is divided into three partitions: Boot and Download Memory, Regular Program Memory, and Data Memory, each with unique data protection schemes. Boot and Download Memory uses 100% redundancy with error monitoring and correction, Regular Program Memory employs error detection with non-maskable interrupts, and Data Memory has optional protection with error detection and external data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 100% redundancy is applied to all memory, then soft error rate is significantly reduced, but memory area and cost increase substantially
Solution Approach 1:
The memory is divided into three distinct partitions (Boot and Download Memory, Regular Program Memory, and Data Memory), each with different protection levels. This segmentation allows applying 100% redundancy only where most critical (Boot and Download Memory) while using lighter protection for less critical areas, thereby reducing overall memory area requirements while maintaining high reliability for essential functions.
Solution Approach 2:
Different memory partitions receive different types and levels of protection according to their relative importance. Boot and Download Memory receives 100% redundancy with error monitoring and correction, while Regular Program Memory and Data Memory receive optional or no redundancy. This local quality approach ensures maximum protection for critical data while minimizing resource consumption for less critical memory areas.
2Reliability
If redundancy is applied to all memory, then data integrity is maximized, but system cost increases
Solution Approach 1:
By segmenting memory into three partitions with different protection requirements, the system applies 100% redundancy only to Boot and Download Memory (most critical), while using cost-effective alternatives for other partitions. This segmentation strategy maximizes data integrity for essential functions while minimizing overall system cost.
Solution Approach 2:
The patent implements local quality by providing different levels of protection at different locations. Critical Boot and Download Memory receives full redundancy protection to ensure data integrity, while less critical areas receive reduced protection, thereby maintaining high reliability where needed and reducing cost elsewhere.
3Reliability
If error detection and correction is implemented in all memory, then soft error rate is reduced, but processing speed decreases due to constant monitoring
Solution Approach 1:
The memory is segmented into three partitions, with error monitoring and correction implemented only in Boot and Download Memory. This segmentation allows the system to maintain high processing speed in data-intensive operations while ensuring reliability for critical boot and download functions, thereby resolving the contradiction between speed and reliability.
Solution Approach 2:
Different quality levels of error protection are applied locally to different memory partitions. Boot and Download Memory receives full error monitoring and correction to ensure reliability, while Regular Program Memory and Data Memory have reduced or no monitoring, maintaining processing speed for non-critical operations.
4Reliability
If system redundancy is implemented, then soft error impact is reduced, but system complexity and cost increase
Solution Approach 1:
The system implements redundancy at the memory partition level rather than system-wide, dividing memory into three distinct partitions with different protection levels. This segmentation approach reduces system complexity by applying redundancy only where most critical (Boot and Download Memory) while maintaining overall system reliability, avoiding the need for complex system-wide redundancy mechanisms.
Solution Approach 2:
The patent applies local quality by implementing different types and levels of protection at different memory locations. Critical Boot and Download Memory receives full redundancy protection to ensure system reliability, while less critical areas receive reduced protection, thereby maintaining reliability where needed without unnecessarily increasing system complexity.
Data Source
AI summary
A method for reducing soft error rates in semiconductor memory. In one embodiment, memory is partitioned into a) boot and download memory, b) program memory and c) data memory. Each partition receives protection according to the importance of the data stored. The boot memory is protected by sensing errors and repairing them utilizing on-chip data storage redundancy and exchange. The program memory is protected by sensing errors and repairing damaged data by reloading it using the program stored in the boot and download memory. The data memory is selectively protected similar to the program memory, but with the added feature of regular saving to disk from which to check for accurate data in the event of corruption. In another embodiment, any or all of the soft error protection features are selectable on a global basis, a memory type basis or, in the cases of program and data memory, on a block level basis.