Segmented Memory Repair Circuit for Smaller Fuse Arrays
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Solution Overview
Problem
Conventional semiconductor memory devices have limited repair capabilities due to hard-wired fuse latch sets, leading to inefficiencies as only a few repair regions per die are utilized, resulting in unused repair elements and resources.
Innovation Solution
The introduction of a segment-address determination circuit that associates repair fuse latch sets with defects rather than redundant elements, allowing for reduced numbers of fuse latches and fuse arrays while maintaining effective repair capabilities by allocating resources based on worst-case defectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hard-wired fuse latch sets are directly coupled to redundant rows and columns, then repair capability is provided, but the number of fuse latches and fuse arrays becomes excessively large with most remaining unused
Solution Approach 1:
The memory array is divided into multiple segments, with each segment having its own dedicated fuse latch set. This segmentation allows the total number of fuse latches to be reduced from what would be required if all redundant elements were served by a single large fuse array, while still providing complete repair coverage. Each segment's fuse latches only need to cover the defects within that segment, not the entire memory array.
Solution Approach 2:
The fuse latch sets are designed to serve multiple purposes: they can repair both row defects and column defects within their segment, and they can work with either spare rows or spare columns depending on which is more efficient. This multi-functionality reduces the total number of fuse latches needed compared to having separate dedicated fuse sets for each repair type.
2Reliability
If redundant rows and columns are allocated for every possible defect scenario, then complete repair coverage is achieved, but most repair elements remain unused
Solution Approach 1:
Instead of allocating repair resources for every possible defect scenario across the entire memory array, the system allocates partial repair resources to each segment. The sum of resources across all segments equals the total needed, but each individual segment uses only what it requires, eliminating the waste of over-provisioning that would occur with a centralized approach.
Solution Approach 2:
Each segment is given repair resources matched to its specific needs rather than every segment receiving the same maximum resources. Segments with higher expected defect rates receive more repair resources, while segments with lower expected defect rates receive fewer resources, optimizing the overall utilization of repair elements.
3Reliability
If fuse array size is increased to cover all potential defects, then repair effectiveness is maintained, but device area and manufacturing cost increase
Solution Approach 1:
The fuse array is divided into multiple smaller segments, each serving a specific portion of the memory array. This segmentation reduces the total area required because each segment only needs to store repair information for its local region, rather than one large fuse array needing to store information for the entire memory array. The sum of the areas of the segmented fuse arrays is less than the area of a single centralized fuse array with equivalent total capacity.
Data Source
AI summary
Methods, apparatuses and systems related to managing access to a memory device are described. A memory device includes fuses and latches for storing a repair segment locator and a repair address for each repair of one or more defective memory cells. A segment-address determination circuit generate an active segment address based on the repair address according to the repair segment locator and an address for a read or a write operation. A comparator circuitry is configured to determine whether the active segment address matches the address for the read or the write operation for replacing the one or more defective memory cells with the plurality of redundant cells when the address for the read/write operation corresponds to the one or more defective memory cells.