Segmented Memory Timing Model Generation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for modeling timing in multi-bit buses introduce unnecessary pessimism, increasing complexity, database size, and cost, and are not applicable to memory compilers due to varying bit lengths across memory instances.
Innovation Solution
The approach involves segmenting buses into a fixed number of sub-buses based on physical architecture and user-defined accuracy, allowing for interpolation of timing models across characterized instances to generate efficient liberty timing files for SoC implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If timing is modeled for each bit of the bus, then timing accuracy is improved, but complexity, database size, and cost are dramatically increased
Solution Approach 1:
The patent divides the multi-bit bus into multiple segments, where each segment contains a subset of bits. Instead of characterizing timing for each individual bit, the bus is segmented into groups (e.g., 4-bit segments), and timing is characterized at the segment level. This segmentation reduces the number of timing models needed while maintaining sufficient accuracy for each segment, thereby reducing overall complexity and database size without completely sacrificing timing precision.
2Measurement precision
If timing is modeled for each bit of the bus, then timing accuracy is improved, but database size and liberty model size are dramatically increased
Solution Approach 1:
The patent segments the bus into multiple groups, reducing the number of individual timing models from one per bit to one per segment. For example, a 32-bit bus is divided into eight 4-bit segments, reducing the number of timing models by a factor of 8. This segmentation directly reduces the quantity of timing data stored in the database and liberty files, decreasing database size while preserving timing accuracy at the segment level.
3Device complexity
If conventional worst case timing model is used for multi-bit bus, then simplicity is maintained, but unnecessary pessimism is introduced in timing models
Solution Approach 1:
The patent applies local quality by characterizing timing for each segment individually rather than using a single worst-case model for the entire bus. Each segment can have its own timing characteristics that reflect its actual performance, allowing for more accurate local timing analysis. This eliminates the unnecessary pessimism introduced by worst-case modeling while maintaining manageable complexity through segment-level rather than bit-level characterization.
4Measurement precision
If timing is modeled for each bit of the bus, then timing detail is improved, but verification cost and generation cost are significantly increased
Solution Approach 1:
The patent segments the bus into manageable groups, reducing the verification effort from verifying each individual bit to verifying each segment. This segmentation maintains sufficient timing detail at the segment level while dramatically reducing the number of verification cases needed. The reduced model complexity and database size resulting from segmentation directly lower both generation cost and verification cost, improving productivity without sacrificing essential timing accuracy.
Data Source
AI summary
Various implementations described herein refer to a method. The method may include selecting a target memory instance to characterize for timing file generation, determining a number of segments for the target memory instance based on user defined accuracy, and partitioning the target memory instance into the number of segments based on a physical architecture of the target memory instance. The method may also include generating test-bench data based on the number of segments and simulating the test-bench data, obtaining simulation data for the target memory instance associated with each segment in the number of segments, and generating a timing file by reporting timing data for each segment in the number of segments.