Segmented Metal Gate Structure to Prevent CMP Over-Polishing
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Solution Overview
Problem
The chemical mechanical polishing process in high-voltage device manufacturing often results in over-polishing of large-area metal gates, leading to negative effects on device performance.
Innovation Solution
A method involving the formation of a dummy gate with polysilicon structures, followed by a protective layer, insulating layer, and metal layer deposition, culminating in chemical mechanical polishing to achieve a planarized metal gate surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If the metal gate area is increased to meet high-voltage device requirements, then the device can achieve the required high voltage performance, but the chemical mechanical polishing process causes over-polishing and dishing phenomenon
Solution Approach 1:
The patent divides the metal gate into multiple segments by creating isolation trenches filled with insulating material. This segmentation reduces the continuous metal gate area into smaller sections, preventing over-polishing while maintaining the overall large-area effect needed for high-voltage performance
Solution Approach 2:
The patent introduces an insulating structure as an intermediary element between metal gate regions. This insulating structure acts as a spacer that prevents direct contact between large metal areas, thereby reducing polishing load and preventing dishing while allowing the metal gate to maintain its large-area configuration for high-voltage operation
2Manufacturing precision
If the metal gate area is reduced to avoid over-polishing, then the dishing phenomenon is prevented, but the high-voltage device cannot achieve the required voltage performance
Solution Approach 1:
By segmenting the metal gate into smaller sections separated by insulating structures, the patent allows each segment to be polished independently without excessive material removal, while the collective arrangement of segments maintains the large effective area needed for high-voltage performance
Solution Approach 2:
The patent solves the area conflict by transitioning to a two-dimensional arrangement where multiple metal gate segments are positioned side-by-side with insulating structures in between, effectively increasing the overall gate width while keeping individual metal areas small enough to avoid over-polishing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method prevents over-polishing while maintaining a large metal gate area, enhancing device performance by eliminating negative effects associated with excessive polishing.
Implementation Method 1
The chemical mechanical polishing process may produce different pattern loadings for metal gates of different sizes
Implementation Method 2
The metal gate manufacturing process usually includes first depositing metal by means of physical vapor deposition (PVD) or chemical vapor deposition (CVD)
Implementation Method 3
The metal gate manufacturing process usually includes first depositing metal by means of physical vapor deposition (PVD) or chemical vapor deposition (CVD)
Data Source
AI summary
The present application provides a metal gate structure of a high-voltage device and a method for making the same, forming a dummy gate on the gate oxide layer, wherein the dummy gate is composed of a plurality of polysilicon structures spaced apart from each other; forming a protective layer on sidewalls of the plurality of polysilicon structures and on the gate oxide layer between the polysilicon structures; performing covering with an insulating layer to fill a region between the polysilicon structures, wherein the filled region forms an insulating structure; removing the polysilicon structure to form a groove; forming a metal layer, wherein the metal layer covers the insulating structure and fills the groove; and polishing the surface of the metal layer, wherein the insulating structure, the protective layer, and the metal layer form a metal gate with a planarized surface.