Segmented Metal Gate for High-Voltage MOS Transistor
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of metal gates in high-voltage MOS transistors, particularly at the 28 nm technology node or beyond, faces challenges such as dishing defects and reduced electrical performance due to aluminum CMP in gate-last processes, leading to poor process yields.
Innovation Solution
A high-voltage MOS transistor design featuring a metal gate composed of discrete segments that are not in direct contact, with each segment being electrically connected through metal layers, and a fabrication method involving a dummy gate process with spacers and dielectric layers to form trenches for the metal gate, allowing for effective integration with high-k metal gate processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If aluminum CMP is used in gate-last process for 28 nm or beyond, then metal gate integration is achieved, but dishing defects occur on large-size gates resulting in poor process yields
Solution Approach 1:
The gate is divided into multiple discrete segments that are not in direct contact with each other. This segmentation allows the gate structure to accommodate CMP-induced dishing without compromising overall gate functionality, as each segment can be independently formed and controlled, preventing the propagation of dishing defects across the entire gate structure.
2Ease of manufacture
If aluminum CMP is used in gate-last process, then metal gate formation is enabled, but electrical performance of HVMOS devices is reduced
Solution Approach 1:
By segmenting the gate structure into discrete non-contacting portions, the patent enables metal gate formation through CMP processes while maintaining electrical performance. The segmentation allows for better control of gate electrode alignment and reduces variability in electrical characteristics across the device.
3Manufacturing precision
If discrete gate segments are used, then gate dishing issues are avoided and electrical performance is enhanced, but process complexity increases
Solution Approach 1:
The gate is segmented into discrete non-contacting segments, which simplifies the formation process by allowing each segment to be independently formed and aligned. This segmentation actually reduces process complexity compared to forming a continuous gate, as it eliminates the need for complex CMP compensation techniques and allows for more straightforward lithographic patterning.
Solution Approach 2:
A spacer structure is introduced as an intermediary element between the discrete gate segments. The spacer serves multiple functions: it defines the spacing between segments, provides structural support, and facilitates the formation process by serving as a template for segment placement. This intermediary structure simplifies the overall fabrication process despite the segmented gate design.
4Device complexity
If continuous gate structure is used, then fabrication process is simpler, but dishing defects and poor yields occur
Solution Approach 1:
The continuous gate structure is replaced with discrete non-contacting segments, which dramatically improves process yield by eliminating dishing defects. Although this may seem to increase fabrication complexity, the segmentation actually simplifies certain process steps such as CMP and lithography, leading to overall improved productivity and yield.
Data Source
AI summary
A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.