Segmented Metallization Structure for Void-Resistant Via Contacts

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Solution Overview

Problem

As semiconductor devices are scaled down, the challenge of forming reliable metallization lines becomes more difficult due to increased complexity and the formation of voids in metal layers, which adversely impact device performance.

Innovation Solution

A method is introduced where a metallization line is formed in an inter-metal dielectric layer, and a metal-cutting operation is performed to segment it into multiple features, which are then filled with a dielectric material to provide isolation, mitigating the gap-filling issues and ensuring device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If metallization lines are formed in scaled-down semiconductor devices, then functional density increases, but voids form in metal layers reducing reliability

Engineering Contradiction:
Improvefunctional densityVSAvoidmetallization line reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The metallization line is segmented into multiple sections by forming isolation trenches between adjacent metallization lines. This segmentation prevents void formation across the entire metallization line and isolates defects to specific segments, thereby maintaining reliability while preserving high functional density in scaled-down devices.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Isolation trenches filled with dielectric material are introduced as intermediary structures between adjacent metallization lines. These isolation trenches act as mediators that prevent direct interaction between neighboring metallization lines, eliminating void formation issues and improving metallization line reliability without reducing functional density.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If feature sizes continue to decrease, then production efficiency increases, but fabrication process complexity increases

Engineering Contradiction:
Improveproduction efficiencyVSAvoidfabrication process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The fabrication process is segmented into distinct stages: forming isolation trenches between metallization lines, filling trenches with dielectric material, and planarizing the surface. This segmentation of the fabrication process makes complex scaled-down device manufacturing more manageable and controllable, reducing overall process complexity while maintaining high production efficiency.

Inventive Principle:
Principle #1Segmentation

3Reliability

If metallization lines are segmented into multiple features, then void formation is reduced, but manufacturing process steps increase

Engineering Contradiction:
Improvemetallization line reliabilityVSAvoidmanufacturing process simplicity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The formation of isolation trenches and the segmentation of metallization lines are merged into a single fabrication step. By patterning both the isolation trenches and metallization line segments simultaneously, the number of manufacturing process steps is reduced while still achieving the reliability benefits of segmentation.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11862559B2Semiconductor structures and methods of forming the same
Publication Date: 2024.01.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11862559B2 patent drawing
  • US11862559B2 patent drawing
  • US11862559B2 patent drawing

AI summary

A semiconductor structure includes a semiconductor substrate, a metallization feature over the semiconductor substrate, a first dielectric feature, a second dielectric feature, and a via contact. The metallization feature includes a first bottom corner and a second bottom corner opposite to the first bottom corner. The first dielectric feature is adjacent to the first bottom corner, and the second dielectric feature is adjacent to the second bottom corner. The metallization feature is interposed between the first dielectric feature and the second dielectric feature. In some embodiments, an included angle of the first bottom corner defined by a sidewall of first dielectric feature and a bottom surface of the metallization feature is less than 90°. The via contact is configured to connect the metallization feature to the semiconductor substrate.