Segmented Fin MOS Gate Layout for Lower Parasitic Resistance
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Solution Overview
Problem
Existing integrated circuit (IC) devices with metal-oxide semiconductor (MOS) transistors face challenges in achieving high performance and high output, particularly in radio-frequency (RF) bands, due to parasitic resistances and limitations in trans-conductance.
Innovation Solution
The IC device incorporates an active region, fin active patterns, a gate pattern, active cutting regions, isolated gate contact regions, and a gate cutting region, which reduces parasitic resistance and increases trans-conductance by applying stress to the MOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOS transistors are highly integrated and downscaled for high integration, then device density increases, but parasitic resistance increases and trans-conductance decreases
Solution Approach 1:
The gate pattern is divided into multiple segments with gate cutting regions between them, allowing independent stress application to each segment. This segmentation enables localized stress optimization without increasing overall parasitic resistance, resolving the contradiction between high integration and parasitic resistance reduction.
Solution Approach 2:
Different regions of the transistor structure are given different properties: isolated gate contact regions provide low-resistance contacts in specific locations, while gate cutting regions apply stress locally to enhance trans-conductance. This local quality differentiation allows high device density while maintaining low parasitic resistance in critical areas.
2Quantity of substance
If MOS transistors are highly integrated and downscaled, then device density increases, but trans-conductance decreases
Solution Approach 1:
Gate cutting regions are formed in advance during manufacturing to pre-apply stress to the channel region. This preliminary stress application enhances trans-conductance before the device operates, allowing high device density to be achieved without sacrificing trans-conductance performance.
Solution Approach 2:
The physical state of the channel region is changed by applying mechanical stress through gate cutting regions. This stress modifies carrier mobility and trans-conductance parameters, enabling high trans-conductance values even in highly integrated, downscaled devices where traditional scaling would reduce performance.
3Ease of manufacture
If gate pattern extends continuously across active region, then manufacturing is simpler, but parasitic resistance increases and trans-conductance decreases
Solution Approach 1:
The continuous gate pattern is segmented into multiple sections with gate cutting regions between them. While this adds manufacturing steps, the segmentation enables stress application and isolated contact formation that dramatically reduce parasitic resistance, making the overall process worthwhile for achieving high-performance RF devices.
Solution Approach 2:
Gate cutting regions act as intermediary structures that provide both mechanical stress application and electrical isolation functions. These intermediary elements enable the transition from a simple continuous gate to a complex segmented structure with reduced parasitic resistance, bridging the gap between manufacturing simplicity and performance optimization.
4Device complexity
If continuous gate pattern is used, then device structure is simpler, but trans-conductance and vibration frequency are limited
Solution Approach 1:
Segmenting the gate pattern into multiple sections with cutting regions enables independent optimization of each segment for stress application and contact isolation. This segmentation increases device complexity but delivers proportional gains in trans-conductance and vibration frequency, making the added complexity necessary for high-performance RF operation.
Solution Approach 2:
The gate structure parameters are changed from continuous to segmented, enabling stress-induced parameter changes in the channel region. This structural parameter change directly enhances trans-conductance and vibration frequency, justifying the increased device complexity for RF applications where these parameters are critical.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances RF performance by increasing trans-conductance, improving cut-off frequency, and maximizing vibration frequency, thereby achieving high output and performance in IC devices.
Implementation Method 1
The gate cutting region, which is spaced apart from the gate pattern on one side of the gate pattern in the first direction, applies stress to increase trans-conductance
Implementation Method 2
an isolated gate contact region in contact with the gate pattern outside of the active region, reducing parasitic resistance
Data Source
AI summary
An integrated circuit device including an active region; an active cutting region at a side of the active region in a first direction; a fin active pattern extending on the active region in the first direction, the fin active pattern including a source region and a drain region; a gate pattern extending across the active region and the fin active pattern in a second direction perpendicular to the first direction, the gate pattern not being in the active cutting region; and an isolated gate contact region in contact with the gate pattern outside of the active region.