Segmented MOSFET Gate Structure With Blocking Dielectric Isolation

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Solution Overview

Problem

As semiconductor devices are scaled down, the operating characteristics of MOSFETs deteriorate, leading to challenges in manufacturing devices with excellent performance while overcoming integration limitations.

Innovation Solution

The semiconductor device incorporates a specific structure with multiple source/drain patterns, semiconductor patterns, a gate dielectric layer, a gate electrode, blocking semiconductor patterns, a blocking dielectric layer, and a blocking electrode, where the blocking dielectric layer consists of distinct material layers to enhance electrical properties and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If MOSFET size is scaled down to increase integration, then device density increases, but operating characteristics deteriorate

Engineering Contradiction:
Improvedevice integration densityVSAvoidoperating characteristics
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The gate electrode is divided into multiple segments (first gate electrode and second gate electrode) separated by a blocking dielectric layer. This segmentation allows independent control of different channel regions, enabling better performance optimization for each segment while maintaining high integration density through compact arrangement.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different dielectric materials are used in different regions: the gate dielectric layer uses a first dielectric material while the blocking dielectric layer uses a second dielectric material with different properties. This local differentiation optimizes electrical characteristics for specific functions - the gate dielectric for charge storage and the blocking dielectric for electrical isolation between gate segments.

Inventive Principle:
Principle #3Local quality

2Area of stationary object

If device size is reduced to improve integration, then area decreases, but electrical properties and reliability worsen

Engineering Contradiction:
Improvedevice areaVSAvoidelectrical properties
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The blocking dielectric layer is positioned vertically between gate electrode segments rather than horizontally, utilizing the vertical dimension for electrical isolation. This allows compact horizontal arrangement for high integration while maintaining adequate electrical separation through the vertical blocking layer structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The device employs a composite dielectric structure with at least two different dielectric materials - a first dielectric material in the gate dielectric layer and a second dielectric material in the blocking dielectric layer. This composite approach combines the beneficial properties of different materials to achieve both small area and excellent electrical characteristics.

Inventive Principle:
Principle #40Composite materials

3Ease of manufacture

If gate dielectric layer uses single material for simplicity, then manufacturing is easier, but threshold voltage control and insulation performance are insufficient

Engineering Contradiction:
Improvedielectric layer fabricationVSAvoidthreshold voltage control
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The dielectric layers utilize different critical parameters - the gate dielectric layer focuses on thickness and material composition for charge storage, while the blocking dielectric layer emphasizes electrical breakdown strength and band alignment for voltage control. By optimizing different parameters for different layers, both manufacturing feasibility and threshold voltage control are achieved.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250142905A1Semiconductor device
Publication Date: 2025.05.01 SAMSUNG ELECTRONICS CO LTD
  • US20250142905A1 patent drawing
  • US20250142905A1 patent drawing
  • US20250142905A1 patent drawing

AI summary

A semiconductor device may include first, second, and third source/drain patterns, semiconductor patterns between the first and third source/drain patterns, a gate dielectric layer in contact with the semiconductor patterns, a gate electrode in contact with the gate dielectric layer, blocking semiconductor patterns between the first and second source/drain patterns, a blocking dielectric layer in contact with the blocking semiconductor patterns, and a blocking electrode in contact with the blocking dielectric layer. The blocking dielectric layer may include a first layer in contact with the first and second source/drain patterns, a second layer in contact with the blocking electrode, and a third layer between the first and second layers. A dielectric material of the third layer may be different than a dielectric material of the first layer and that of the second layer.