Segmented Multiplexing Circuit for Lower Output Delay
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Solution Overview
Problem
Conventional multiplexing circuits experience increased load and output delay as the number of input signals increases, leading to potential erroneous operations in downstream circuits due to the need for additional selection circuits and increased load on the selection circuit.
Innovation Solution
A multiplexing circuit with a separate multiplexing structure comprising multiple multiplexing units and a multiplexing output unit, where each unit is initialized by a shared initialization signal and performs logic operations on selection output signals to reduce load and output delay, with each unit receiving the selection control signal of its neighboring unit as an initialization signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of input signals increases, then the selection capability of the multiplexing circuit is improved, but the load on the selection circuit increases and output delay time increases
Solution Approach 1:
The multiplexing circuit is divided into multiple sub-multiplexing units (first, second, third, fourth sub-multiplexing units) that process different groups of input signals separately. Each sub-unit handles a subset of the total input signals, reducing the load on individual selection circuits. The outputs of these sub-units are then combined through logical operations to produce the final output, thereby maintaining high selection capability while reducing output delay time.
2Adaptability or versatility
If the number of input signals increases, then the selection capability of the multiplexing circuit is improved, but the load on the selection circuit increases
Solution Approach 1:
The circuit is segmented into multiple sub-multiplexing units, each handling a specific group of input signals. This segmentation distributes the computational load across multiple smaller circuits rather than concentrating it in a single large selection circuit, thereby reducing the load on each individual selection circuit while maintaining the ability to select from all input signals.
Solution Approach 2:
The outputs of the multiple sub-multiplexing units are merged through logical operations (such as OR operations) to produce the final output signal. This merging approach allows the circuit to maintain high selection capability by combining the results from multiple parallel processing paths, effectively handling a large number of input signals without requiring a single complex selection circuit.
Data Source
AI summary
Disclosed herein is a multiplexing circuit for decreasing the output delay time of an output signal. The multiplexing circuit includes multiplexing units and a multiplexing output unit. Each multiplexing unit is initialized in response to an initialization signal, and outputs an input signal as a selection output signal in response to a selection control signal. The multiplexing output unit performs a logic operation on selection output signals received from the multiplexing units and outputs a multiplexing output signal based on the results of this operation. Preferably, the initialization signal is shared by two of the multiplexing units, and the initialization signal which is input to one of the two multiplexing units is the selection control signal which in input to the other of the two multiplexing units.