Segmented Multiplier Architecture for Iterative Arithmetic Refinement
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Solution Overview
Problem
The scheduling of arithmetic operations in processors is challenged by the need to perform iterative refinement for divide and square root operations, which conflicts with regular multiplications due to differing latency requirements.
Innovation Solution
The implementation of both a full-precision large multiplier and a reduced-precision small multiplier, along with control logic to manage their usage, allows for efficient iterative refinement in arithmetic units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a single full-precision multiplier is used for all operations, then manufacturing cost and area are reduced, but latency for iterative refinement operations increases
Solution Approach 1:
The multiplier is segmented into two distinct units: a full-precision large multiplier for high-precision operations and a reduced-precision small multiplier for initial approximations. This segmentation allows each unit to be optimized for its specific function, with the small multiplier having lower latency and the large multiplier providing full precision when needed.
Solution Approach 2:
The small multiplier performs partial multiplication with reduced precision for initial approximation, which is sufficient for the first iteration of Newton-Raphson. This partial action is then followed by refinement using the large multiplier, achieving the desired precision without requiring the small multiplier to perform complete high-precision operations.
2Productivity
If a reduced-precision small multiplier is added, then latency for initial approximation is reduced, but device complexity and area increase
Solution Approach 1:
The multiplier functionality is segmented into two independent units with different precision levels. The small multiplier handles initial approximation operations at reduced precision, while the large multiplier handles refinement operations at full precision. This segmentation enables optimized performance for each operation type without requiring the entire system to operate at maximum precision always.
Solution Approach 2:
The small multiplier provides sufficient precision for the initial approximation step (partial action), which is all that is needed for the first iteration. This partial precision approach reduces the computational burden and latency for initial operations, with full precision being applied only when necessary through the large multiplier in subsequent iterations.
3Adaptability or versatility
If iterative refinement is performed using a single multiplier, then device complexity is minimized, but scheduling conflicts arise between different operation types
Solution Approach 1:
The multiplier is segmented into specialized units: a small multiplier dedicated to initial approximation operations and a large multiplier dedicated to refinement operations. This segmentation eliminates scheduling conflicts by assigning different operations to appropriate units based on their precision requirements, allowing independent execution without interference.
Solution Approach 2:
The control unit provides multi-functionality by directing operations to either the small or large multiplier based on the operation type and precision requirements. The small multiplier serves initial approximation for divide and square root operations, while the large multiplier handles refinement operations and regular multiplications, creating a universal system that adapts to different computational needs.
Data Source
AI summary
In an aspect, a processor includes circuitry for iterative refinement approaches, e.g., Newton-Raphson, to evaluating functions, such as square root, reciprocal, and for division. The circuitry includes circuitry for producing an initial approximation; which can include a LookUp Table (LUT). LUT may produce an output that (with implementation-dependent processing) forms an initial approximation of a value, with a number of bits of precision. A limited-precision multiplier multiplies that initial approximation with another value; an output of the limited precision multiplier goes to a full precision multiplier circuit that performs remaining multiplications required for iteration(s) in the particular refinement process being implemented. For example, in division, the output being calculated is for a reciprocal of the divisor. The full-precision multiplier circuit requires a first number of clock cycles to complete, and both the small multiplier and the initial approximation circuitry complete within the first number of clock cycles.