Segmented Charge-Trap NAND Stack for Better Data Retention
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Solution Overview
Problem
Conventional NAND memory architectures face data retention issues due to charge migration between memory cells caused by charge-trapping material extending across multiple cells, leading to inefficiencies in charge storage and retrieval.
Innovation Solution
Incorporating breaks in the charge-trapping material between memory cells and employing a vertical stack of alternating insulative and conductive levels with tailored gate structures to impede charge migration, thereby controlling charge storage and retrieval effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If charge-trapping material is used to extend across multiple memory cells, then charge storage capacity is improved, but data retention deteriorates due to charge migration between cells
Solution Approach 1:
The charge-trapping material is segmented into discrete portions, with each portion associated with a specific memory cell rather than extending continuously across multiple cells. This segmentation prevents charge migration between cells while maintaining adequate charge storage capacity within each cell's designated portion.
Solution Approach 2:
The harmful continuous extension of charge-trapping material across multiple cells is extracted/removed. Instead, only the necessary portion of charge-trapping material is retained within each cell's boundaries, eliminating the source of charge migration while preserving charge storage functionality.
2Quantity of substance
If vertically-stacked memory cells are implemented, then packing density is improved, but charge migration between cells increases
Solution Approach 1:
In the vertically-stacked architecture, the charge-trapping material is segmented into discrete portions at different vertical levels, with each portion confined to its respective memory cell. This vertical segmentation maintains high packing density through stacking while preventing lateral charge migration between adjacent cells through the segmentation isolation.
Solution Approach 2:
The charge-trapping material is placed only in specific local regions corresponding to individual memory cells rather than extending continuously. Each local portion has the necessary charge storage properties, while the localized placement prevents harmful charge migration to neighboring cells, enabling both high density and data retention.
3Ease of manufacture
If continuous charge-trapping material is used across multiple cells, then manufacturing simplicity is maintained, but charge storage efficiency deteriorates
Solution Approach 1:
The charge-trapping material is formed as segmented portions through standard semiconductor fabrication processes. The segmentation can be achieved through conventional patterning and deposition techniques, maintaining manufacturing simplicity while improving charge storage efficiency by confining charge to specific cell regions.
Solution Approach 2:
The physical parameters of the charge-trapping material are optimized: instead of a thin continuous layer, segmented portions with controlled thickness and volume are formed. This parameter change increases the effective charge storage capacity within each cell while the segmented structure prevents charge loss to neighboring cells.
Data Source
AI summary
Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include terminal regions, and include nonterminal regions proximate the terminal regions. The terminal regions are vertically thicker than the nonterminal regions, and are configured as segments which are vertically stacked one atop another and which are vertically spaced from one another. Blocks are adjacent to the segments and have approximately a same vertical thickness as the segments. The blocks include high-k dielectric material, charge-blocking material and charge-storage material. Channel material extends vertically along the stack and is adjacent to the blocks. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.